[llvm] a2938ba - [RISCV] Add tests that m extension enabled in extractelt-int-rv64.ll. NFC.

[Jim Lin via llvm-commits]

Author: Jim Lin
Date: 2023-08-03T15:34:44+08:00
New Revision: a2938ba70727e29e66a20584499ba4e016aedeb6

URL: https://github.com/llvm/llvm-project/commit/a2938ba70727e29e66a20584499ba4e016aedeb6
DIFF: https://github.com/llvm/llvm-project/commit/a2938ba70727e29e66a20584499ba4e016aedeb6.diff

LOG: [RISCV] Add tests that m extension enabled in extractelt-int-rv64.ll. NFC.

It has been added in extractelt-int-rv32.ll.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
index 52594807353c50..6430db2680825e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN:     -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64NOM
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64M
 
 define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv1i8_0:
@@ -738,15 +740,24 @@ define i32 @extractelt_sub_nxv4i32_splat(<vscale x 4 x i32> %x) {
 }
 
 define i32 @extractelt_mul_nxv4i32_splat(<vscale x 4 x i32> %x) {
-; CHECK-LABEL: extractelt_mul_nxv4i32_splat:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    li a0, 3
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT:    vmul.vx v8, v8, a0
-; CHECK-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
-; CHECK-NEXT:    vslidedown.vi v8, v8, 3
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    ret
+; RV64NOM-LABEL: extractelt_mul_nxv4i32_splat:
+; RV64NOM:       # %bb.0:
+; RV64NOM-NEXT:    li a0, 3
+; RV64NOM-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; RV64NOM-NEXT:    vmul.vx v8, v8, a0
+; RV64NOM-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
+; RV64NOM-NEXT:    vslidedown.vi v8, v8, 3
+; RV64NOM-NEXT:    vmv.x.s a0, v8
+; RV64NOM-NEXT:    ret
+;
+; RV64M-LABEL: extractelt_mul_nxv4i32_splat:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
+; RV64M-NEXT:    vslidedown.vi v8, v8, 3
+; RV64M-NEXT:    vmv.x.s a0, v8
+; RV64M-NEXT:    slli a1, a0, 1
+; RV64M-NEXT:    addw a0, a1, a0
+; RV64M-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %bo = mul <vscale x 4 x i32> %x, %splat
@@ -755,16 +766,28 @@ define i32 @extractelt_mul_nxv4i32_splat(<vscale x 4 x i32> %x) {
 }
 
 define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
-; CHECK-LABEL: extractelt_sdiv_nxv4i32_splat:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a0, 349525
-; CHECK-NEXT:    addiw a0, a0, 1366
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT:    vmulh.vx v8, v8, a0
-; CHECK-NEXT:    vsrl.vi v10, v8, 31
-; CHECK-NEXT:    vadd.vv v8, v8, v10
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    ret
+; RV64NOM-LABEL: extractelt_sdiv_nxv4i32_splat:
+; RV64NOM:       # %bb.0:
+; RV64NOM-NEXT:    lui a0, 349525
+; RV64NOM-NEXT:    addiw a0, a0, 1366
+; RV64NOM-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; RV64NOM-NEXT:    vmulh.vx v8, v8, a0
+; RV64NOM-NEXT:    vsrl.vi v10, v8, 31
+; RV64NOM-NEXT:    vadd.vv v8, v8, v10
+; RV64NOM-NEXT:    vmv.x.s a0, v8
+; RV64NOM-NEXT:    ret
+;
+; RV64M-LABEL: extractelt_sdiv_nxv4i32_splat:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    vsetivli zero, 0, e32, m2, ta, ma
+; RV64M-NEXT:    vmv.x.s a0, v8
+; RV64M-NEXT:    lui a1, 349525
+; RV64M-NEXT:    addiw a1, a1, 1366
+; RV64M-NEXT:    mul a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 63
+; RV64M-NEXT:    srli a0, a0, 32
+; RV64M-NEXT:    addw a0, a0, a1
+; RV64M-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %bo = sdiv <vscale x 4 x i32> %x, %splat
@@ -773,16 +796,28 @@ define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
 }
 
 define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
-; CHECK-LABEL: extractelt_udiv_nxv4i32_splat:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a0, 349525
-; CHECK-NEXT:    addiw a0, a0, 1366
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT:    vmulh.vx v8, v8, a0
-; CHECK-NEXT:    vsrl.vi v10, v8, 31
-; CHECK-NEXT:    vadd.vv v8, v8, v10
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    ret
+; RV64NOM-LABEL: extractelt_udiv_nxv4i32_splat:
+; RV64NOM:       # %bb.0:
+; RV64NOM-NEXT:    lui a0, 349525
+; RV64NOM-NEXT:    addiw a0, a0, 1366
+; RV64NOM-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; RV64NOM-NEXT:    vmulh.vx v8, v8, a0
+; RV64NOM-NEXT:    vsrl.vi v10, v8, 31
+; RV64NOM-NEXT:    vadd.vv v8, v8, v10
+; RV64NOM-NEXT:    vmv.x.s a0, v8
+; RV64NOM-NEXT:    ret
+;
+; RV64M-LABEL: extractelt_udiv_nxv4i32_splat:
+; RV64M:       # %bb.0:
+; RV64M-NEXT:    vsetivli zero, 0, e32, m2, ta, ma
+; RV64M-NEXT:    vmv.x.s a0, v8
+; RV64M-NEXT:    lui a1, 349525
+; RV64M-NEXT:    addiw a1, a1, 1366
+; RV64M-NEXT:    mul a0, a0, a1
+; RV64M-NEXT:    srli a1, a0, 63
+; RV64M-NEXT:    srli a0, a0, 32
+; RV64M-NEXT:    addw a0, a0, a1
+; RV64M-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %bo = sdiv <vscale x 4 x i32> %x, %splat