[PATCH] D156642: libunwind: riscv: disable vector test when csr instructions aren't present

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


================
Comment at: libunwind/src/Registers.hpp:4107
     reg_t vlenb;
     __asm__("csrr %0, 0xC22" : "=r"(vlenb));
     return vlenb;
----------------
Another alternative is using `.insn` for this to prevent any dependency of extension, this should be generally OK since when program hit there means vector extension is enabled, which means `csrr ` is available, and AArch64 has use this trick in their libgcc implementation[1], although I guess their intention is compatibility issue with older binutils , but I think we could use same trick.

This might be more robust implantation since we also treat UNW_RISCV_VLENB as valid register in other place like line 4088.

So I think either: 
1) Check with __riscv_zicsr for UNW_RISCV_VLENB, but also check all other use site for UNW_RISCV_VLENB.
2) Use `.insn`.

[1] https://github.com/gcc-mirror/gcc/blob/master/libgcc/config/aarch64/value-unwind.h#L38


Repository:
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https://reviews.llvm.org/D156642