[llvm] 97cccdd - [LV][NFC] Remove the redundant braces.

Mel Chen via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 2 20:45:34 PDT 2023


Author: Mel Chen
Date: 2023-08-02T20:45:04-07:00
New Revision: 97cccdd9f3c5d250cf0031c84ec363c96fa94321

URL: https://github.com/llvm/llvm-project/commit/97cccdd9f3c5d250cf0031c84ec363c96fa94321
DIFF: https://github.com/llvm/llvm-project/commit/97cccdd9f3c5d250cf0031c84ec363c96fa94321.diff

LOG: [LV][NFC] Remove the redundant braces.

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 8bbcf7750c8916..db0591e757a663 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -3993,10 +3993,10 @@ void InnerLoopVectorizer::fixReduction(VPReductionPHIRecipe *PhiR,
     Builder.setFastMathFlags(RdxDesc.getFastMathFlags());
     for (unsigned Part = 1; Part < UF; ++Part) {
       Value *RdxPart = State.get(LoopExitInstDef, Part);
-      if (Op != Instruction::ICmp && Op != Instruction::FCmp) {
+      if (Op != Instruction::ICmp && Op != Instruction::FCmp)
         ReducedPartRdx = Builder.CreateBinOp(
             (Instruction::BinaryOps)Op, RdxPart, ReducedPartRdx, "bin.rdx");
-      } else if (RecurrenceDescriptor::isSelectCmpRecurrenceKind(RK))
+      else if (RecurrenceDescriptor::isSelectCmpRecurrenceKind(RK))
         ReducedPartRdx = createSelectCmpOp(Builder, ReductionStartValue, RK,
                                            ReducedPartRdx, RdxPart);
       else


        


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