[llvm] 6676027 - [RISCV] Implement support for bf16 select when zfbfmin is enabled
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 2 12:05:13 PDT 2023
Author: Alex Bradbury
Date: 2023-08-02T20:04:30+01:00
New Revision: 667602793bef72e64367ac46cbaf96e3afaea22e
URL: https://github.com/llvm/llvm-project/commit/667602793bef72e64367ac46cbaf96e3afaea22e
DIFF: https://github.com/llvm/llvm-project/commit/667602793bef72e64367ac46cbaf96e3afaea22e.diff
LOG: [RISCV] Implement support for bf16 select when zfbfmin is enabled
These test cases previously caused an error. RISCVInstrInfo::copyPhysReg also needed a tweak in order to account for copying bf16 values in FPR16 registers.
Differential Revision: https://reviews.llvm.org/D156883
Added:
llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 79e2d8d756d65f..ddd06d129a08d2 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -376,6 +376,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
setOperationAction(ISD::ConstantFP, MVT::bf16, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::bf16, Expand);
+ setOperationAction(ISD::SELECT, MVT::bf16, Promote);
+ setOperationAction(ISD::SETCC, MVT::bf16, Promote);
}
if (Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin()) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index e0cbca6dc1c203..8b419c720022b3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -330,9 +330,10 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
if (STI.hasStdExtZfh()) {
Opc = RISCV::FSGNJ_H;
} else {
- assert(STI.hasStdExtF() && STI.hasStdExtZfhmin() &&
+ assert(STI.hasStdExtF() &&
+ (STI.hasStdExtZfhmin() || STI.hasStdExtZfbfmin()) &&
"Unexpected extensions");
- // Zfhmin subset doesn't have FSGNJ_H, replaces FSGNJ_H with FSGNJ_S.
+ // Zfhmin/Zfbfmin doesn't have FSGNJ_H, replace FSGNJ_H with FSGNJ_S.
DstReg = TRI->getMatchingSuperReg(DstReg, RISCV::sub_16,
&RISCV::FPR32RegClass);
SrcReg = TRI->getMatchingSuperReg(SrcReg, RISCV::sub_16,
diff --git a/llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll b/llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
new file mode 100644
index 00000000000000..8335e5430f34ed
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
@@ -0,0 +1,327 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin -verify-machineinstrs \
+; RUN: -target-abi ilp32f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin -verify-machineinstrs \
+; RUN: -target-abi lp64f < %s | FileCheck %s
+
+define bfloat @select_fcmp_false(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_false:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fmv.s fa0, fa1
+; CHECK-NEXT: ret
+ %1 = fcmp false bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_oeq(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_oeq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: feq.s a0, fa5, fa4
+; CHECK-NEXT: bnez a0, .LBB1_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp oeq bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_ogt(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_ogt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: flt.s a0, fa4, fa5
+; CHECK-NEXT: bnez a0, .LBB2_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp ogt bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_oge(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_oge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: fle.s a0, fa4, fa5
+; CHECK-NEXT: bnez a0, .LBB3_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB3_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp oge bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_olt(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_olt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: flt.s a0, fa5, fa4
+; CHECK-NEXT: bnez a0, .LBB4_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB4_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp olt bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_ole(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_ole:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fle.s a0, fa5, fa4
+; CHECK-NEXT: bnez a0, .LBB5_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB5_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp ole bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_one(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_one:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: flt.s a0, fa5, fa4
+; CHECK-NEXT: flt.s a1, fa4, fa5
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: bnez a0, .LBB6_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB6_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp one bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_ord(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_ord:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: feq.s a0, fa5, fa5
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: feq.s a1, fa4, fa4
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: bnez a0, .LBB7_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa4, fa5
+; CHECK-NEXT: .LBB7_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa4
+; CHECK-NEXT: ret
+ %1 = fcmp ord bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_ueq(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_ueq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: flt.s a0, fa5, fa4
+; CHECK-NEXT: flt.s a1, fa4, fa5
+; CHECK-NEXT: or a0, a1, a0
+; CHECK-NEXT: beqz a0, .LBB8_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB8_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp ueq bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_ugt(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_ugt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fle.s a0, fa5, fa4
+; CHECK-NEXT: beqz a0, .LBB9_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB9_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp ugt bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_uge(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_uge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: flt.s a0, fa5, fa4
+; CHECK-NEXT: beqz a0, .LBB10_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB10_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp uge bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_ult(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_ult:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: fle.s a0, fa4, fa5
+; CHECK-NEXT: beqz a0, .LBB11_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB11_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp ult bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_ule(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_ule:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: flt.s a0, fa4, fa5
+; CHECK-NEXT: beqz a0, .LBB12_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB12_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp ule bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_une(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_une:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: feq.s a0, fa5, fa4
+; CHECK-NEXT: beqz a0, .LBB13_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: .LBB13_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = fcmp une bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_uno(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_uno:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: feq.s a0, fa5, fa5
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: feq.s a1, fa4, fa4
+; CHECK-NEXT: and a0, a1, a0
+; CHECK-NEXT: beqz a0, .LBB14_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fmv.s fa4, fa5
+; CHECK-NEXT: .LBB14_2:
+; CHECK-NEXT: fcvt.bf16.s fa0, fa4
+; CHECK-NEXT: ret
+ %1 = fcmp uno bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+define bfloat @select_fcmp_true(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_true:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ret
+ %1 = fcmp true bfloat %a, %b
+ %2 = select i1 %1, bfloat %a, bfloat %b
+ ret bfloat %2
+}
+
+; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
+define i32 @i32_select_fcmp_oeq(bfloat %a, bfloat %b, i32 %c, i32 %d) nounwind {
+; CHECK-LABEL: i32_select_fcmp_oeq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: feq.s a2, fa4, fa5
+; CHECK-NEXT: bnez a2, .LBB16_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: mv a0, a1
+; CHECK-NEXT: .LBB16_2:
+; CHECK-NEXT: ret
+ %1 = fcmp oeq bfloat %a, %b
+ %2 = select i1 %1, i32 %c, i32 %d
+ ret i32 %2
+}
+
+define i32 @select_fcmp_oeq_1_2(bfloat %a, bfloat %b) {
+; CHECK-LABEL: select_fcmp_oeq_1_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: feq.s a0, fa4, fa5
+; CHECK-NEXT: li a1, 2
+; CHECK-NEXT: sub a0, a1, a0
+; CHECK-NEXT: ret
+ %1 = fcmp fast oeq bfloat %a, %b
+ %2 = select i1 %1, i32 1, i32 2
+ ret i32 %2
+}
+
+define signext i32 @select_fcmp_uge_negone_zero(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_uge_negone_zero:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: fle.s a0, fa4, fa5
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: ret
+ %1 = fcmp ugt bfloat %a, %b
+ %2 = select i1 %1, i32 -1, i32 0
+ ret i32 %2
+}
+
+define signext i32 @select_fcmp_uge_1_2(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: select_fcmp_uge_1_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: fle.s a0, fa4, fa5
+; CHECK-NEXT: addi a0, a0, 1
+; CHECK-NEXT: ret
+ %1 = fcmp ugt bfloat %a, %b
+ %2 = select i1 %1, i32 1, i32 2
+ ret i32 %2
+}
diff --git a/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll b/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
new file mode 100644
index 00000000000000..5009468b4e2b51
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
@@ -0,0 +1,205 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin -verify-machineinstrs \
+; RUN: -target-abi ilp32f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin -verify-machineinstrs \
+; RUN: -target-abi lp64f < %s | FileCheck %s
+
+define bfloat @select_icmp_eq(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
+; CHECK-LABEL: select_icmp_eq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a0, a1, .LBB0_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = icmp eq i32 %a, %b
+ %2 = select i1 %1, bfloat %c, bfloat %d
+ ret bfloat %2
+}
+
+define bfloat @select_icmp_ne(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
+; CHECK-LABEL: select_icmp_ne:
+; CHECK: # %bb.0:
+; CHECK-NEXT: bne a0, a1, .LBB1_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = icmp ne i32 %a, %b
+ %2 = select i1 %1, bfloat %c, bfloat %d
+ ret bfloat %2
+}
+
+define bfloat @select_icmp_ugt(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
+; CHECK-LABEL: select_icmp_ugt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: bltu a1, a0, .LBB2_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = icmp ugt i32 %a, %b
+ %2 = select i1 %1, bfloat %c, bfloat %d
+ ret bfloat %2
+}
+
+define bfloat @select_icmp_uge(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
+; CHECK-LABEL: select_icmp_uge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: bgeu a0, a1, .LBB3_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB3_2:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = icmp uge i32 %a, %b
+ %2 = select i1 %1, bfloat %c, bfloat %d
+ ret bfloat %2
+}
+
+define bfloat @select_icmp_ult(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
+; CHECK-LABEL: select_icmp_ult:
+; CHECK: # %bb.0:
+; CHECK-NEXT: bltu a0, a1, .LBB4_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB4_2:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = icmp ult i32 %a, %b
+ %2 = select i1 %1, bfloat %c, bfloat %d
+ ret bfloat %2
+}
+
+define bfloat @select_icmp_ule(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
+; CHECK-LABEL: select_icmp_ule:
+; CHECK: # %bb.0:
+; CHECK-NEXT: bgeu a1, a0, .LBB5_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB5_2:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = icmp ule i32 %a, %b
+ %2 = select i1 %1, bfloat %c, bfloat %d
+ ret bfloat %2
+}
+
+define bfloat @select_icmp_sgt(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
+; CHECK-LABEL: select_icmp_sgt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: blt a1, a0, .LBB6_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB6_2:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = icmp sgt i32 %a, %b
+ %2 = select i1 %1, bfloat %c, bfloat %d
+ ret bfloat %2
+}
+
+define bfloat @select_icmp_sge(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
+; CHECK-LABEL: select_icmp_sge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: bge a0, a1, .LBB7_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB7_2:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = icmp sge i32 %a, %b
+ %2 = select i1 %1, bfloat %c, bfloat %d
+ ret bfloat %2
+}
+
+define bfloat @select_icmp_slt(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
+; CHECK-LABEL: select_icmp_slt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: blt a0, a1, .LBB8_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB8_2:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = icmp slt i32 %a, %b
+ %2 = select i1 %1, bfloat %c, bfloat %d
+ ret bfloat %2
+}
+
+define bfloat @select_icmp_sle(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
+; CHECK-LABEL: select_icmp_sle:
+; CHECK: # %bb.0:
+; CHECK-NEXT: bge a1, a0, .LBB9_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB9_2:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %1 = icmp sle i32 %a, %b
+ %2 = select i1 %1, bfloat %c, bfloat %d
+ ret bfloat %2
+}
+
+define bfloat @select_icmp_slt_one(i32 signext %a) {
+; CHECK-LABEL: select_icmp_slt_one:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slti a0, a0, 1
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: lui a1, %hi(.LCPI10_0)
+; CHECK-NEXT: addi a1, a1, %lo(.LCPI10_0)
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: flh fa0, 0(a0)
+; CHECK-NEXT: ret
+ %1 = icmp slt i32 %a, 1
+ %2 = select i1 %1, bfloat 1.000000e+00, bfloat 0.000000e+00
+ ret bfloat %2
+}
+
+define bfloat @select_icmp_sgt_zero(i32 signext %a) {
+; CHECK-LABEL: select_icmp_sgt_zero:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sgtz a0, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: lui a1, %hi(.LCPI11_0)
+; CHECK-NEXT: addi a1, a1, %lo(.LCPI11_0)
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: flh fa0, 0(a0)
+; CHECK-NEXT: ret
+ %1 = icmp sgt i32 %a, 0
+ %2 = select i1 %1, bfloat 0.000000e+00, bfloat 1.000000e+00
+ ret bfloat %2
+}
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