[PATCH] D156909: [RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:3241
   SmallVector<SDValue, 8> Ops;
+
   // Skip the merge operand at index 0 if !UseTUPseudo.
----------------
Stray change


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:3595
+/// steps issues with MachineCSE not being able to CSE expressions with
+/// IMPLICIT_DEF operands while preserving the semantic intend. Note
+/// that this transform is the last one performed at ISEL DAG to DAG.
----------------
intend -> intent?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:57
+///   Otherwise, policy operand and tablegen flags drive the interpretation.
+///   (If policy operand is not present - there are a couple, thought we're
+///   rapidly removing them - a non-undefined policy defaults to "tail
----------------
thought -> though?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156909/new/

https://reviews.llvm.org/D156909