[llvm] 1e7c79d - [FPEnv][InstCombine] Correct strictfp tests.
Kevin P. Neal via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 2 10:03:26 PDT 2023
Author: Kevin P. Neal
Date: 2023-08-02T13:03:10-04:00
New Revision: 1e7c79d3627f2a9f3bc95cb7edc7570fdec6c71b
URL: https://github.com/llvm/llvm-project/commit/1e7c79d3627f2a9f3bc95cb7edc7570fdec6c71b
DIFF: https://github.com/llvm/llvm-project/commit/1e7c79d3627f2a9f3bc95cb7edc7570fdec6c71b.diff
LOG: [FPEnv][InstCombine] Correct strictfp tests.
Correct InstCombine strictfp tests to follow the rules documented
in the LangRef:
https://llvm.org/docs/LangRef.html#constrained-floating-point-intrinsics
Mostly these tests just needed the strictfp attribute on function
definitions. After D154991 the constrained intrinsics have the
strictfp attribute by default so they don't need it here, but other
functions do.
Test changes verified with D146845.
Added:
Modified:
llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
llvm/test/Transforms/InstCombine/is_fpclass.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
index 3075dae55010b6..9413258d67b0ba 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
@@ -682,7 +682,7 @@ define i1 @test_class_isnan_f32(float %x) nounwind {
ret i1 %val
}
-define i1 @test_class_isnan_f32_strict(float %x) nounwind {
+define i1 @test_class_isnan_f32_strict(float %x) nounwind strictfp {
; CHECK-LABEL: @test_class_isnan_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3) #[[ATTR16:[0-9]+]]
; CHECK-NEXT: ret i1 [[VAL]]
@@ -700,7 +700,7 @@ define i1 @test_class_is_p0_n0_f32(float %x) nounwind {
ret i1 %val
}
-define i1 @test_class_is_p0_n0_f32_strict(float %x) nounwind {
+define i1 @test_class_is_p0_n0_f32_strict(float %x) nounwind strictfp {
; CHECK-LABEL: @test_class_is_p0_n0_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96) #[[ATTR16]]
; CHECK-NEXT: ret i1 [[VAL]]
@@ -5624,7 +5624,7 @@ define double @trig_preop_constfold() {
ret double %val
}
-define double @trig_preop_constfold_strictfp() {
+define double @trig_preop_constfold_strictfp() strictfp {
; CHECK-LABEL: @trig_preop_constfold_strictfp(
; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 5) #[[ATTR16]]
; CHECK-NEXT: ret double [[VAL]]
diff --git a/llvm/test/Transforms/InstCombine/is_fpclass.ll b/llvm/test/Transforms/InstCombine/is_fpclass.ll
index b9371287a68421..36ba988e2b332a 100644
--- a/llvm/test/Transforms/InstCombine/is_fpclass.ll
+++ b/llvm/test/Transforms/InstCombine/is_fpclass.ll
@@ -105,7 +105,7 @@ define <2 x i1> @test_class_isnan_v2f32(<2 x float> %x) {
ret <2 x i1> %val
}
-define i1 @test_class_isnan_f32_strict(float %x) {
+define i1 @test_class_isnan_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_isnan_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3) #[[ATTR6:[0-9]+]]
; CHECK-NEXT: ret i1 [[VAL]]
@@ -331,7 +331,7 @@ define <2 x i1> @test_class_is_not_p0_n0_v2f32(<2 x float> %x) {
ret <2 x i1> %val
}
-define i1 @test_class_is_not_p0_n0_f32_strict(float %x) {
+define i1 @test_class_is_not_p0_n0_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_not_p0_n0_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 927) #[[ATTR6]]
; CHECK-NEXT: ret i1 [[VAL]]
@@ -385,7 +385,7 @@ define i1 @test_class_is_not_p0_n0_psub_nsub_f32_dynamic(float %x) "denormal-fp-
ret i1 %val
}
-define i1 @test_class_is_p0_n0_f32_strict(float %x) {
+define i1 @test_class_is_p0_n0_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_p0_n0_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96) #[[ATTR6]]
; CHECK-NEXT: ret i1 [[VAL]]
@@ -565,7 +565,7 @@ define i1 @test_class_is_inf_or_nan_f32(float %x) {
ret i1 %val
}
-define i1 @test_class_is_pinf_f32_strict(float %x) {
+define i1 @test_class_is_pinf_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_pinf_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 512) #[[ATTR6]]
; CHECK-NEXT: ret i1 [[VAL]]
@@ -574,7 +574,7 @@ define i1 @test_class_is_pinf_f32_strict(float %x) {
ret i1 %val
}
-define i1 @test_class_is_ninf_f32_strict(float %x) {
+define i1 @test_class_is_ninf_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_ninf_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 4) #[[ATTR6]]
; CHECK-NEXT: ret i1 [[VAL]]
@@ -583,7 +583,7 @@ define i1 @test_class_is_ninf_f32_strict(float %x) {
ret i1 %val
}
-define i1 @test_class_is_inf_f32_strict(float %x) {
+define i1 @test_class_is_inf_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_inf_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 516) #[[ATTR6]]
; CHECK-NEXT: ret i1 [[VAL]]
@@ -592,7 +592,7 @@ define i1 @test_class_is_inf_f32_strict(float %x) {
ret i1 %val
}
-define i1 @test_class_is_pinf_or_nan_f32_strict(float %x) {
+define i1 @test_class_is_pinf_or_nan_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_pinf_or_nan_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 515) #[[ATTR6]]
; CHECK-NEXT: ret i1 [[VAL]]
@@ -601,7 +601,7 @@ define i1 @test_class_is_pinf_or_nan_f32_strict(float %x) {
ret i1 %val
}
-define i1 @test_class_is_ninf_or_nan_f32_strict(float %x) {
+define i1 @test_class_is_ninf_or_nan_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_ninf_or_nan_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 7) #[[ATTR6]]
; CHECK-NEXT: ret i1 [[VAL]]
@@ -610,7 +610,7 @@ define i1 @test_class_is_ninf_or_nan_f32_strict(float %x) {
ret i1 %val
}
-define i1 @test_class_is_inf_or_nan_f32_strict(float %x) {
+define i1 @test_class_is_inf_or_nan_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_inf_or_nan_f32_strict(
; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 519) #[[ATTR6]]
; CHECK-NEXT: ret i1 [[VAL]]
@@ -851,7 +851,7 @@ define i1 @test_class_is_not_nan_nnan_src(float %x) {
ret i1 %class
}
-define i1 @test_class_is_not_nan_nnan_src_strict(float %x) {
+define i1 @test_class_is_not_nan_nnan_src_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_not_nan_nnan_src_strict(
; CHECK-NEXT: ret i1 true
;
@@ -911,7 +911,7 @@ define i1 @test_class_is_not_inf_ninf_src(float %x) {
ret i1 %class
}
-define i1 @test_class_is_not_inf_ninf_src_strict(float %x) {
+define i1 @test_class_is_not_inf_ninf_src_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_not_inf_ninf_src_strict(
; CHECK-NEXT: ret i1 true
;
@@ -2073,7 +2073,7 @@ define i1 @test_class_fabs_posinf_negnormal_possubnormal_negzero_snan_strictfp(f
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 661) #[[ATTR6]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
- %fabs = call float @llvm.fabs.f32(float %arg)
+ %fabs = call float @llvm.fabs.f32(float %arg) strictfp
%class = call i1 @llvm.is.fpclass.f32(float %fabs, i32 681) strictfp
ret i1 %class
}
@@ -2403,7 +2403,7 @@ define i1 @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_snan_stric
; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 361) #[[ATTR6]]
; CHECK-NEXT: ret i1 [[CLASS]]
;
- %fabs = call float @llvm.fabs.f32(float %arg)
+ %fabs = call float @llvm.fabs.f32(float %arg) strictfp
%fneg.fabs = fneg float %fabs
%class = call i1 @llvm.is.fpclass.f32(float %fneg.fabs, i32 681) strictfp
ret i1 %class
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