[PATCH] D155299: [AArch64][SVE2] Combine add+lsr to rshrnb for stores
Matt Devereau via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 2 04:27:13 PDT 2023
MattDevereau updated this revision to Diff 546405.
MattDevereau added a comment.
Emit an AArch64ISD node instead of the machine node directly.
Include D->S addressing mode of RSHRNB
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155299/new/
https://reviews.llvm.org/D155299
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll
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