[PATCH] D156868: [ARM] Permit VGETLNi32 and VSETLNi32 without mnemonic suffix.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham updated this revision to Diff 546401.
simon_tatham added a comment.

Correction: using `NEONInstAlias` was a mistake because it meant the
aliases had stricter requirements than the instructions they map to.
The revised version of the patch gives each alias the same
requirements as its base instruction. For example, these aliases are
now accepted in `thumbv7m` as well as `armv8a`.

I'm a bit worried to find that those requirements are //different//,
though. `VSETLNi32` simply requires `HasVFP2`, whereas `VGETLNi32`
requires both `HasFPRegs` and `HasFastVGETLNi32`. I would have thought
that the matching get and set operations ought to be enabled by the
same feature! And surely `HasFastVGETLNi32` only ought to be
conditionalizing the //selection// of `VGETLNi32` during compilation,
and shouldn't also make it illegal to write by hand in assembler.

But those are probably things to fix in a separate patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156868/new/

https://reviews.llvm.org/D156868

Files:
  llvm/lib/Target/ARM/ARMInstrNEON.td
  llvm/test/MC/ARM/neon-mov-encoding.s


Index: llvm/test/MC/ARM/neon-mov-encoding.s
===================================================================
--- llvm/test/MC/ARM/neon-mov-encoding.s
+++ llvm/test/MC/ARM/neon-mov-encoding.s
@@ -110,23 +110,27 @@
 	vmov.u8		r0, d16[1]
 	vmov.u16	r0, d16[1]
 	vmov.32		r0, d16[1]
+	vmov    	r0, d16[1]
 	vmov.8	d16[1], r1
 	vmov.16	d16[1], r1
 	vmov.32	d16[1], r1
 	vmov.8	d18[1], r1
 	vmov.16	d18[1], r1
 	vmov.32	d18[1], r1
+	vmov   	d18[1], r1
 
 @ CHECK: vmov.s8	r0, d16[1]      @ encoding: [0xb0,0x0b,0x50,0xee]
 @ CHECK: vmov.s16	r0, d16[1]      @ encoding: [0xf0,0x0b,0x10,0xee]
 @ CHECK: vmov.u8	r0, d16[1]      @ encoding: [0xb0,0x0b,0xd0,0xee]
 @ CHECK: vmov.u16	r0, d16[1]      @ encoding: [0xf0,0x0b,0x90,0xee]
 @ CHECK: vmov.32	r0, d16[1]      @ encoding: [0x90,0x0b,0x30,0xee]
+@ CHECK: vmov.32	r0, d16[1]      @ encoding: [0x90,0x0b,0x30,0xee]
 @ CHECK: vmov.8	d16[1], r1              @ encoding: [0xb0,0x1b,0x40,0xee]
 @ CHECK: vmov.16	d16[1], r1      @ encoding: [0xf0,0x1b,0x00,0xee]
 @ CHECK: vmov.32	d16[1], r1      @ encoding: [0x90,0x1b,0x20,0xee]
 @ CHECK: vmov.8	d18[1], r1              @ encoding: [0xb0,0x1b,0x42,0xee]
 @ CHECK: vmov.16	d18[1], r1      @ encoding: [0xf0,0x1b,0x02,0xee]
+@ CHECK: vmov.32	d18[1], r1      @ encoding: [0x90,0x1b,0x22,0xee]
 @ CHECK: vmov.32	d18[1], r1      @ encoding: [0x90,0x1b,0x22,0xee]
 
 
Index: llvm/lib/Target/ARM/ARMInstrNEON.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrNEON.td
+++ llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -6396,6 +6396,10 @@
                 Requires<[HasFPRegs, HasFastVGETLNi32]> {
   let Inst{21} = lane{0};
 }
+// VGETLNi32 is also legal as just vmov r0,d0[0] without the .32 suffix
+def : InstAlias<"vmov${p} $R, $V$lane",
+    (VGETLNi32 GPR:$R, DPR:$V, VectorIndex32:$lane, pred:$p)>,
+    Requires<[HasFPRegs, HasFastVGETLNi32]>;
 let Predicates = [HasNEON] in {
 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
 def : Pat<(ARMvgetlanes (v16i8 QPR:$src), imm:$lane),
@@ -6538,6 +6542,9 @@
   let isInsertSubreg = 1;
 }
 }
+// VSETLNi32 is also legal as just vmov d0[0],r0 without the .32 suffix
+def : VFP2InstAlias<"vmov${p} $V$lane, $R",
+    (VSETLNi32 DPR:$V, GPR:$R, VectorIndex32:$lane, pred:$p)>;
 
 // TODO: for odd lanes we could optimize this a bit by using the VINS
 // FullFP16 instruction when it is available


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