[PATCH] D153278: [RISCV] Add test for un-maskable pseudo without policy operand
Luke Lau via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 2 03:59:49 PDT 2023
luke updated this revision to Diff 546397.
luke added a comment.
Rebase
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D153278/new/
https://reviews.llvm.org/D153278
Files:
llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
Index: llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
+++ llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
@@ -90,3 +90,31 @@
ret <vscale x 1 x i8> %a
}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
+ <vscale x 1 x i1>,
+ <vscale x 1 x float>,
+ <vscale x 1 x float>,
+ <vscale x 1 x i1>,
+ iXLen);
+
+; FIXME: Make sure we preserve the passthrough on mask pseudos without policy
+; operands
+define <vscale x 1 x i1> @test4(ptr %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) {
+; CHECK-LABEL: test4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
+; CHECK-NEXT: vmflt.vv v0, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
+ iXLen %3);
+ %passthru = load <vscale x 1 x i1>, ptr %0
+ %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
+ <vscale x 1 x i1> %passthru,
+ <vscale x 1 x float> %1,
+ <vscale x 1 x float> %2,
+ <vscale x 1 x i1> %allone,
+ iXLen %3)
+ ret <vscale x 1 x i1> %a
+}
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