[PATCH] D156868: [ARM] Permit VGETLNi32 and VSETLNi32 without mnemonic suffix.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
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These instructions transfer 32 bits of data between an integer
register and half of a d-register. Currently LLVM accepts them only
with the syntax `vmov.32 r0, d0[0]` or `vmov.32 d0[0], r0`. But the
ARMARM says that the `.32` suffix on the mnemonic should be optional.

Added a pair of NEONInstAlias to accept the bare `vmov` version, and
checked that the result is the same as with `.32`.

This only adds new syntax accepted in assembly. The existing explicit
version is still used when disassembling these instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156868

Files:
  llvm/lib/Target/ARM/ARMInstrNEON.td
  llvm/test/MC/ARM/neon-mov-encoding.s


Index: llvm/test/MC/ARM/neon-mov-encoding.s
===================================================================
--- llvm/test/MC/ARM/neon-mov-encoding.s
+++ llvm/test/MC/ARM/neon-mov-encoding.s
@@ -110,23 +110,27 @@
 	vmov.u8		r0, d16[1]
 	vmov.u16	r0, d16[1]
 	vmov.32		r0, d16[1]
+	vmov    	r0, d16[1]
 	vmov.8	d16[1], r1
 	vmov.16	d16[1], r1
 	vmov.32	d16[1], r1
 	vmov.8	d18[1], r1
 	vmov.16	d18[1], r1
 	vmov.32	d18[1], r1
+	vmov   	d18[1], r1
 
 @ CHECK: vmov.s8	r0, d16[1]      @ encoding: [0xb0,0x0b,0x50,0xee]
 @ CHECK: vmov.s16	r0, d16[1]      @ encoding: [0xf0,0x0b,0x10,0xee]
 @ CHECK: vmov.u8	r0, d16[1]      @ encoding: [0xb0,0x0b,0xd0,0xee]
 @ CHECK: vmov.u16	r0, d16[1]      @ encoding: [0xf0,0x0b,0x90,0xee]
 @ CHECK: vmov.32	r0, d16[1]      @ encoding: [0x90,0x0b,0x30,0xee]
+@ CHECK: vmov.32	r0, d16[1]      @ encoding: [0x90,0x0b,0x30,0xee]
 @ CHECK: vmov.8	d16[1], r1              @ encoding: [0xb0,0x1b,0x40,0xee]
 @ CHECK: vmov.16	d16[1], r1      @ encoding: [0xf0,0x1b,0x00,0xee]
 @ CHECK: vmov.32	d16[1], r1      @ encoding: [0x90,0x1b,0x20,0xee]
 @ CHECK: vmov.8	d18[1], r1              @ encoding: [0xb0,0x1b,0x42,0xee]
 @ CHECK: vmov.16	d18[1], r1      @ encoding: [0xf0,0x1b,0x02,0xee]
+@ CHECK: vmov.32	d18[1], r1      @ encoding: [0x90,0x1b,0x22,0xee]
 @ CHECK: vmov.32	d18[1], r1      @ encoding: [0x90,0x1b,0x22,0xee]
 
 
Index: llvm/lib/Target/ARM/ARMInstrNEON.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrNEON.td
+++ llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -6396,6 +6396,9 @@
                 Requires<[HasFPRegs, HasFastVGETLNi32]> {
   let Inst{21} = lane{0};
 }
+// VGETLNi32 is also legal as just vmov r0,d0[0] without the .32 suffix
+def : NEONInstAlias<"vmov${p} $R, $V$lane",
+    (VGETLNi32 GPR:$R, DPR:$V, VectorIndex32:$lane, pred:$p)>;
 let Predicates = [HasNEON] in {
 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
 def : Pat<(ARMvgetlanes (v16i8 QPR:$src), imm:$lane),
@@ -6538,6 +6541,9 @@
   let isInsertSubreg = 1;
 }
 }
+// VSETLNi32 is also legal as just vmov d0[0],r0 without the .32 suffix
+def : NEONInstAlias<"vmov${p} $V$lane, $R",
+    (VSETLNi32 DPR:$V, GPR:$R, VectorIndex32:$lane, pred:$p)>;
 
 // TODO: for odd lanes we could optimize this a bit by using the VINS
 // FullFP16 instruction when it is available


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