[PATCH] D151414: [RISCV] Add Zvfhmin extension support for llvm RISCV backend.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added a comment.

In D151414#4552579 <https://reviews.llvm.org/D151414#4552579>, @michaelmaitland wrote:

> In D151414#4552577 <https://reviews.llvm.org/D151414#4552577>, @jacquesguan wrote:
>
>> In D151414#4552130 <https://reviews.llvm.org/D151414#4552130>, @michaelmaitland wrote:
>>
>>> If I add RUN line with `zvfhmin` instead of `zvfh` `llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll`, the compiler gives `LLVM ERROR: Cannot select: t31: nxv1f32 = RISCVISD::VFWNMADD_VL t2, t4, t6, t8, t13`, followed by trace.  Probably need to check for zvfh in `performVFMADD_VLCombine`? Also maybe need to check in other functions like `performFADDSUB_VLCombine`?
>>
>> Thanks to point it. I add a check to prevent the combination to widen op when we have only zvfhmin. But these test can not pass with RUN line zvfhmin because the vf form need promotion of splat, when implement in https://reviews.llvm.org/D153848.
>
> Should this patch depend on the type promotion patch then?

No, actually the type promotion patch depends on this one. This patch added the basic support of zvfhmin which can only select to the several supported type convert instruction. https://reviews.llvm.org/D153848 uses promotion to support other ops.


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