[PATCH] D156846: [RISCV] Add CFI information for vector callee-saved registers
Brandon Wu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 1 19:48:09 PDT 2023
4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, armkevincheng, sjarus, eric-k256, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson, qcolombet, MatzeB.
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4vtomat requested review of this revision.
Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay.
Herald added a project: LLVM.
Currently the CFI offset for RVV registers are not handled entirely,
this patch add those information for either stack unwinding or
debugger to work correctly on RVV callee-saved stack object.
Depends On D154576 <https://reviews.llvm.org/D154576>
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D156846
Files:
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/lib/Target/RISCV/RISCVFrameLowering.h
llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
llvm/test/CodeGen/RISCV/rvv-cfi-info.ll
llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
llvm/test/CodeGen/RISCV/rvv/localvar.ll
llvm/test/CodeGen/RISCV/rvv/memory-args.ll
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
llvm/test/CodeGen/RISCV/rvv/round-vp.ll
llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vpstore.ll
llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
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