[PATCH] D138809: [RISCV] Support vector crypto extension LLVM IR

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7187
+  return Subtarget.getRealMinVLen() *
+             VT.getSizeInBits().getKnownMinValue() / 64 >=
+         EGS * VT.getScalarSizeInBits();
----------------
craig.topper wrote:
> Use `RVVBitsPerBlock` instead of 64
Please add extra parentheses to `Subtarget.getRealMinVLen() * VT.getSizeInBits().getKnownMinValue() / 64` to make the operator precedence clear


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138809/new/

https://reviews.llvm.org/D138809