[llvm] 1f0d24c - update_llc_test_checks: Fix broken amdgpu test
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 1 17:00:28 PDT 2023
Author: Matt Arsenault
Date: 2023-08-01T20:00:21-04:00
New Revision: 1f0d24ce24e92ed69f949d6974b87a10af27bd2b
URL: https://github.com/llvm/llvm-project/commit/1f0d24ce24e92ed69f949d6974b87a10af27bd2b
DIFF: https://github.com/llvm/llvm-project/commit/1f0d24ce24e92ed69f949d6974b87a10af27bd2b.diff
LOG: update_llc_test_checks: Fix broken amdgpu test
Use the correct address space for alloca. Also use opaque pointers.
Added:
Modified:
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Removed:
################################################################################
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll
index 1d8db1ecbc3621..eabcbcbc795286 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll
@@ -1,31 +1,31 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s
define i64 @i64_test(i64 %i) nounwind readnone {
- %loc = alloca i64
- %j = load i64, i64 * %loc
+ %loc = alloca i64, addrspace(5)
+ %j = load i64, ptr addrspace(5) %loc
%r = add i64 %i, %j
ret i64 %r
}
define i64 @i32_test(i32 %i) nounwind readnone {
- %loc = alloca i32
- %j = load i32, i32 * %loc
+ %loc = alloca i32, addrspace(5)
+ %j = load i32, ptr addrspace(5) %loc
%r = add i32 %i, %j
%ext = zext i32 %r to i64
ret i64 %ext
}
define i64 @i16_test(i16 %i) nounwind readnone {
- %loc = alloca i16
- %j = load i16, i16 * %loc
+ %loc = alloca i16, addrspace(5)
+ %j = load i16, ptr addrspace(5) %loc
%r = add i16 %i, %j
%ext = zext i16 %r to i64
ret i64 %ext
}
define i64 @i8_test(i8 %i) nounwind readnone {
- %loc = alloca i8
- %j = load i8, i8 * %loc
+ %loc = alloca i8, addrspace(5)
+ %j = load i8, ptr addrspace(5) %loc
%r = add i8 %i, %j
%ext = zext i8 %r to i64
ret i64 %ext
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
index 38c20409191d75..d1d722a213e300 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
@@ -10,8 +10,8 @@ define i64 @i64_test(i64 %i) nounwind readnone {
; CHECK-NEXT: t13: ch,glue = CopyToReg t11, Register:i32 $vgpr1, t17, t11:1
; CHECK-NEXT: t14: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t13, t13:1
; CHECK-EMPTY:
- %loc = alloca i64
- %j = load i64, i64 * %loc
+ %loc = alloca i64, addrspace(5)
+ %j = load i64, ptr addrspace(5) %loc
%r = add i64 %i, %j
ret i64 %r
}
@@ -25,8 +25,8 @@ define i64 @i32_test(i32 %i) nounwind readnone {
; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
; CHECK-EMPTY:
- %loc = alloca i32
- %j = load i32, i32 * %loc
+ %loc = alloca i32, addrspace(5)
+ %j = load i32, ptr addrspace(5) %loc
%r = add i32 %i, %j
%ext = zext i32 %r to i64
ret i64 %ext
@@ -41,8 +41,8 @@ define i64 @i16_test(i16 %i) nounwind readnone {
; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
; CHECK-EMPTY:
- %loc = alloca i16
- %j = load i16, i16 * %loc
+ %loc = alloca i16, addrspace(5)
+ %j = load i16, ptr addrspace(5) %loc
%r = add i16 %i, %j
%ext = zext i16 %r to i64
ret i64 %ext
@@ -57,8 +57,8 @@ define i64 @i8_test(i8 %i) nounwind readnone {
; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
; CHECK-EMPTY:
- %loc = alloca i8
- %j = load i8, i8 * %loc
+ %loc = alloca i8, addrspace(5)
+ %j = load i8, ptr addrspace(5) %loc
%r = add i8 %i, %j
%ext = zext i8 %r to i64
ret i64 %ext
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