[PATCH] D156831: [AArch64][GlobalISel] Legalize integer across-lane intrinsics with actual type

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h:328-341
+    // trunc(sext x) -> x
+    Register SextSrc;
+    if (mi_match(SrcReg, MRI, m_GSExt(m_Reg(SextSrc)))) {
+      LLT DstTy = MRI.getType(DstReg);
+      LLT SextSrcTy = MRI.getType(SextSrc);
+      if (DstTy == SextSrcTy) {
+        LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
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This should be a separate patch from the AArch64 changes


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156831/new/

https://reviews.llvm.org/D156831