[PATCH] D156801: [RISCV] Improve codegen for i8/i16 'atomicrmw xchg a, {0,-1}'
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 1 14:09:14 PDT 2023
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.
LGTM with that comment addressed.
I had tried to do this as part of in `widenPartwordAtomicRMW` in AtomicExpandPass.cpp. That regressed in VE which has a pretty capable xchg instruction with builtin masking but not and/or. After that failed attempt I was going to write basically this patch, but you beat me to it. Thanks.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:16752
+ isa<ConstantInt>(AI->getValOperand())) {
+ ConstantInt *CVal = static_cast<ConstantInt *>(AI->getValOperand());
+ if (CVal->isZero())
----------------
static_cast -> cast. I know you already did `isa` but `cast` is the llvm way.
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https://reviews.llvm.org/D156801/new/
https://reviews.llvm.org/D156801
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