[PATCH] D156709: [RISCVRVVInitUndef] Ignore tied use for partial undef register

[Philip Reames via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1e86abc914bb: [RISCVRVVInitUndef] Ignore tied use for partial undef register (authored by reames).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156709/new/

https://reviews.llvm.org/D156709

Files:
  llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
  llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

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