[PATCH] D155484: [AArch64] Global Isel Funnel Shift Lowering

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:1032-1034
+  APInt Amount = APInt(64, MI.getOpcode() == TargetOpcode::G_FSHL
+                       ? BitWidth - VRegAndVal->Value.getSExtValue()
+                       : VRegAndVal->Value.getSExtValue(), true);
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Can just construct without the =


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Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:1036-1064
+  // If the instruction is G_FSHR, has a 64-bit G_CONSTANT for shift amount
+  // in the range of 0 <-> BitWidth, it is legal
+  if (ShiftTy.getSizeInBits() == 64 &&
+      MI.getOpcode() == TargetOpcode::G_FSHR && 
+      Amount.ult(BitWidth) &&
+      Amount.uge(0)) {
+    return true;
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Could this just be an optimization combine instead? You're ultimately just falling back to the default legalization


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155484/new/

https://reviews.llvm.org/D155484