[PATCH] D156105: [AMDGPU][True16] Support generating differently-sized register transfers.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev updated this revision to Diff 546005.
kosarev added a comment.

Change the commit title as suggested and remove the unused code handling
the non-True16 case along with the test covering it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156105/new/

https://reviews.llvm.org/D156105

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/VOP1Instructions.td
  llvm/test/CodeGen/AMDGPU/lo16-32bit-physreg-copy.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D156105.546005.patch
Type: text/x-patch
Size: 6551 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230801/3bccdb1b/attachment.bin>