[llvm] 80cd505 - [CSKY] Optimize implementation of intrinsic 'llvm.cttz.i32'

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2023-08-01T17:12:32+08:00
New Revision: 80cd505914dfc2f38f57341f9bef9d208fdc238e

URL: https://github.com/llvm/llvm-project/commit/80cd505914dfc2f38f57341f9bef9d208fdc238e
DIFF: https://github.com/llvm/llvm-project/commit/80cd505914dfc2f38f57341f9bef9d208fdc238e.diff

LOG: [CSKY] Optimize implementation of intrinsic 'llvm.cttz.i32'

Reviewed By: zixuan-wu

Differential Revison: https://reviews.llvm.org/D154588

Added: 
    

Modified: 
    llvm/lib/Target/CSKY/CSKYISelLowering.cpp
    llvm/lib/Target/CSKY/CSKYInstrInfo.td
    llvm/test/CodeGen/CSKY/intrinsic.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
index 5d21aab513ddee..d10d7ccb0bb6a7 100644
--- a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
@@ -59,7 +59,6 @@ CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::UREM, MVT::i32, Expand);
   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
-  setOperationAction(ISD::CTTZ, MVT::i32, Expand);
   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
   setOperationAction(ISD::ROTR, MVT::i32, Expand);
   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
@@ -103,6 +102,7 @@ CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
   if (!Subtarget.has2E3()) {
     setOperationAction(ISD::ABS, MVT::i32, Expand);
     setOperationAction(ISD::BITREVERSE, MVT::i32, Expand);
+    setOperationAction(ISD::CTTZ, MVT::i32, Expand);
     setOperationAction(ISD::SDIV, MVT::i32, Expand);
     setOperationAction(ISD::UDIV, MVT::i32, Expand);
   }

diff  --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.td b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
index 549c883c34a729..70b83c6392ce95 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
@@ -1429,6 +1429,7 @@ let Predicates = [iHasE2] in {
   let Predicates = [iHas2E3] in {
     def : Pat<(bitreverse GPR:$rx), (BREV32 GPR:$rx)>;
     def : Pat<(bswap GPR:$rx), (REVB32 GPR:$rx)>;
+    def : Pat<(i32 (cttz GPR:$rx)), (FF1 (BREV32 GPR:$rx))>;
   }
   def : Pat<(i32 (ctlz GPR:$rx)), (FF1 GPR:$rx)>;
 }

diff  --git a/llvm/test/CodeGen/CSKY/intrinsic.ll b/llvm/test/CodeGen/CSKY/intrinsic.ll
index efe2f8bfb8a956..cd006e726de573 100644
--- a/llvm/test/CodeGen/CSKY/intrinsic.ll
+++ b/llvm/test/CodeGen/CSKY/intrinsic.ll
@@ -11,6 +11,33 @@ entry:
   ret i32 %nlz
 }
 
+define i32 @cttz_0(i32 %x) {
+; CHECK-LABEL: cttz_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bez32 a0, .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %cond.false
+; CHECK-NEXT:    brev32 a0, a0
+; CHECK-NEXT:    ff1.32 a0, a0
+; CHECK-NEXT:    rts16
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    movi16 a0, 32
+; CHECK-NEXT:    rts16
+entry:
+  %ntz = call i32 @llvm.cttz.i32(i32 %x, i1 0)
+  ret i32 %ntz
+}
+
+define i32 @cttz_1(i32 %x) {
+; CHECK-LABEL: cttz_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    brev32 a0, a0
+; CHECK-NEXT:    ff1.32 a0, a0
+; CHECK-NEXT:    rts16
+entry:
+  %ntz = call i32 @llvm.cttz.i32(i32 %x, i1 1)
+  ret i32 %ntz
+}
+
 define i32 @bswap(i32 %x) {
 ; CHECK-LABEL: bswap:
 ; CHECK:       # %bb.0: # %entry
@@ -33,4 +60,5 @@ entry:
 
 declare i32 @llvm.bswap.i32(i32)
 declare i32 @llvm.ctlz.i32 (i32, i1)
+declare i32 @llvm.cttz.i32 (i32, i1)
 declare i32 @llvm.bitreverse.i32(i32)