[PATCH] D138809: [RISCV] Support vector crypto extension LLVM IR

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7135
+static inline bool isValidEGW(int EGS, EVT VT) {
+  return VT.getSizeInBits().getKnownMinValue() >= EGS * VT.getScalarSizeInBits();
+}
----------------
4vtomat wrote:
> craig.topper wrote:
> > Doesn't this need to consider the value of vscale or VLEN? getKnownMinValue() always returns 64 for <vscale x 2 x i32>.
> My thought was: For each `<vscale x N x M>`, if `N * M >= EGS * M == [4|8] * M`, namely if `N >= EGS`, then it's valid.
> So, for vaesdf.vv vd, vs1, vs2, <vscale x 2 x i32> is invalid, however, <vscale x 4 x i32> and larger is valid.
<vscale x 4 x i32> is LMUL=2. I thought based on our conversation here https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234#discussion_r1271843685 that we wanted to allow LMUL=1 with Zvl128b?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138809/new/

https://reviews.llvm.org/D138809