[PATCH] D155041: [RISCV] Remove unnecessary move of undefined with subregister liveness enabled

Mon Jul 31 22:47:45 PDT 2023

BeMg planned changes to this revision.
BeMg added a comment.

In D155041#4547839 <https://reviews.llvm.org/D155041#4547839>, @craig.topper wrote:

> Is this related to https://github.com/llvm/llvm-project/issues/63554?

Yes.

In D155041#4547368 <https://reviews.llvm.org/D155041#4547368>, @reames wrote:

> Can you take a step back and describe what the motivating code here is?  The description on the change seems to start from a level of detail, which makes it hard to reverse back to your motivation.  I think you must be seeing overly constrained register allocation on some example, but which example?
>
> Also, you may find https://reviews.llvm.org/D156709 partially addresses the same issue.  Not sure as without the original example, or something reasonable illustrative, it's hard to tell what you're trying to do here.

Originally, I observed some `insert_subreg` that generate from init-undef pass will be transform into COPY and it can't be eliminated by the following optimization pass. I thought if we could have a RISC-V own `insert_subreg` node, then we could manual eliminated it from MIR precisely. It make sure there are not extra instruction from init-undef pass.

Now D156709 <https://reviews.llvm.org/D156709> shows that redundant COPY come from unnecessary undef register fix-up, so those `insert_subreg` I observed is unnecessary too.

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I will investigate whether there are any reasonable testcase can be resolved by this patch.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155041/new/

https://reviews.llvm.org/D155041