[PATCH] D156692: [RISCV] Scalarize binop followed by extractelement to W instruction on RV64

Mon Jul 31 18:49:48 PDT 2023

Jim marked an inline comment as done.
Jim added a comment.

In D156692#4547870 <https://reviews.llvm.org/D156692#4547870>, @craig.topper wrote:

> It's not clear to me this should be restricted to i64 and i32 either. An i16 or i8 `add` for example doesn't require any extra code unless the result needs to be sign/zero extended.

It doesn't need to be restricted to i64 or i32 either. i32 type ALU operation on RV64 is one of cases here (Maybe is only case in all of tests we had now).
The change of this patch is if any type is not legal, but its operation action is set to custom. That we permit a vector binary operation can be converted to it. (one of cases here is vadd for element type i32 can be converted to addw).
Thanks for your feedback.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156692/new/

https://reviews.llvm.org/D156692