[PATCH] D156104: [AMDGPU] Switch to using real True16 operands.

[Joe Nash via Phabricator via llvm-commits]

Joe_Nash added inline comments.


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Comment at: llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt:60
 
-# GFX11: v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff]
+# GFX11: v_add_f16_dpp v5.l, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff]
 0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff
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kosarev wrote:
> Joe_Nash wrote:
> > Why has only the dst changed to a 16 bit register?
> The DPP source operand fields in `VOPProfile_True16` still refer to the Fake16 operands.
The disassembler changes in this patch include:

  - Some non-complete subset of the total number of 16-bit instructions are converted to True16, such that when disassembled they will have .h and .l suffixes on their operands. The other instructions remain unchanged. This seems fairly uncontroversial to me. It looks like there is no disassembly coverage of the .h operands; can some of the downstream tests be added to this patch? 

- Some operands of instructions have been converted to True16, while others have not. This results in disassembler output where some operands of the instruction explicitly have the .lo suffix, where some do not have that suffix but are implicitly lo. I think there is some potential for confusion in the users here, so all the operands should be transitioned simultaneously.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156104/new/

https://reviews.llvm.org/D156104