[llvm] f92dc10 - [RISCV] Add a common base class for RVInstI variations. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 31 13:08:01 PDT 2023
Author: Craig Topper
Date: 2023-07-31T13:03:35-07:00
New Revision: f92dc1083285f682ba9a858b8566823e6e449f6a
URL: https://github.com/llvm/llvm-project/commit/f92dc1083285f682ba9a858b8566823e6e449f6a
DIFF: https://github.com/llvm/llvm-project/commit/f92dc1083285f682ba9a858b8566823e6e449f6a.diff
LOG: [RISCV] Add a common base class for RVInstI variations. NFC
We have multiple variations of InstrFormatI that pack different
fields into the upper 12 bits. The other 20 bits are all the same.
Add base class to capture this commonality and allow subclasses to
explicitly define Inst{31-20}.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D156589
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index fefa54343cd57f..f8f4150aa727fe 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -357,62 +357,51 @@ class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
let Inst{6-0} = opcode.Value;
}
-class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
- string opcodestr, string argstr>
+// Common base class for I format instructions. Bits {31-20} should be set by
+// the subclasses.
+class RVInstIBase<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
- bits<12> imm12;
bits<5> rs1;
bits<5> rd;
- let Inst{31-20} = imm12;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
let Inst{6-0} = opcode.Value;
}
+class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
+ bits<12> imm12;
+
+ let Inst{31-20} = imm12;
+}
+
class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
dag outs, dag ins, string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
+ : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
bits<6> shamt;
- bits<5> rs1;
- bits<5> rd;
let Inst{31-27} = imm11_7;
let Inst{26} = 0;
let Inst{25-20} = shamt;
- let Inst{19-15} = rs1;
- let Inst{14-12} = funct3;
- let Inst{11-7} = rd;
- let Inst{6-0} = opcode.Value;
}
class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
dag outs, dag ins, string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
+ : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
bits<5> shamt;
- bits<5> rs1;
- bits<5> rd;
let Inst{31-25} = imm11_5;
let Inst{24-20} = shamt;
- let Inst{19-15} = rs1;
- let Inst{14-12} = funct3;
- let Inst{11-7} = rd;
- let Inst{6-0} = opcode.Value;
}
class RVInstIUnary<bits<12> imm12, bits<3> funct3, RISCVOpcode opcode,
dag outs, dag ins, string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
- bits<5> rs1;
- bits<5> rd;
-
+ : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
let Inst{31-20} = imm12;
- let Inst{19-15} = rs1;
- let Inst{14-12} = funct3;
- let Inst{11-7} = rd;
- let Inst{6-0} = opcode.Value;
}
class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index ad461184418588..b6623def0fcbd6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -13,10 +13,12 @@
let DecoderNamespace = "XCVbitmanip" in {
class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
string opcodestr, string argstr>
- : RVInstI<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
+ : RVInstIBase<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
bits<5> is3;
bits<5> is2;
- let imm12 = {funct2, is3, is2};
+ let Inst{31-30} = funct2;
+ let Inst{29-25} = is3;
+ let Inst{24-20} = is2;
}
class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr,
@@ -194,18 +196,13 @@ let DecoderNamespace = "XCValu" in {
(ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
class CVInstAluRI<bits<7> funct7, bits<3> funct3, string opcodestr>
- : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5), opcodestr,
- "$rd, $rs1, $imm5", [], InstFormatOther> {
+ : RVInstIBase<funct3, OPC_CUSTOM_1, (outs GPR:$rd),
+ (ins GPR:$rs1, uimm5:$imm5), opcodestr,
+ "$rd, $rs1, $imm5"> {
bits<5> imm5;
- bits<5> rs1;
- bits<5> rd;
let Inst{31-25} = funct7;
let Inst{24-20} = imm5;
- let Inst{19-15} = rs1;
- let Inst{14-12} = funct3;
- let Inst{11-7} = rd;
- let Inst{6-0} = OPC_CUSTOM_1.Value;
}
class CVInstAluR<bits<7> funct7, bits<3> funct3, string opcodestr>
@@ -316,19 +313,13 @@ class CVInstSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode,
dag outs, dag ins, string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
bits<6> imm6;
- bits<5> rs1;
- bits<5> rd;
let Inst{31-27} = funct5;
let Inst{26} = F;
let Inst{25} = imm6{0}; // funct1 unused
let Inst{24-20} = imm6{5-1};
- let Inst{19-15} = rs1;
- let Inst{14-12} = funct3;
- let Inst{11-7} = rd;
- let Inst{6-0} = opcode.Value;
let DecoderNamespace = "XCVsimd";
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
index 8d18143595e1d1..a9d72b47a7f175 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -87,9 +87,9 @@ class THShift_ri<bits<5> funct5, bits<3> funct3, string opcodestr>
opcodestr, "$rd, $rs1, $shamt">;
class THBitfieldExtract_rii<bits<3> funct3, string opcodestr>
- : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
- (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
- opcodestr, "$rd, $rs1, $msb, $lsb"> {
+ : RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
+ (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
+ opcodestr, "$rd, $rs1, $msb, $lsb"> {
bits<6> msb;
bits<6> lsb;
let Inst{31-26} = msb;
@@ -184,14 +184,14 @@ class THLoadIndexed<RegisterClass Ty, bits<5> funct5, string opcodestr>
}
class THLoadUpdate<bits<5> funct5, string opcodestr>
- : RVInstI<0b100, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
- (ins GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
- opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
+ : RVInstIBase<0b100, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
+ (ins GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
+ opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
bits<5> simm5;
bits<2> uimm2;
- let imm12{11-7} = funct5;
- let imm12{6-5} = uimm2;
- let imm12{4-0} = simm5;
+ let Inst{31-27} = funct5;
+ let Inst{26-25} = uimm2;
+ let Inst{24-20} = simm5;
let Constraints = "@earlyclobber $rd, $rs1_wb = $rs1";
}
}
@@ -206,14 +206,14 @@ class THStoreIndexed<RegisterClass StTy, bits<5> funct5, string opcodestr>
}
class THStoreUpdate<bits<5> funct5, string opcodestr>
- : RVInstI<0b101, OPC_CUSTOM_0, (outs GPR:$rs1_up),
- (ins GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
- opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
+ : RVInstIBase<0b101, OPC_CUSTOM_0, (outs GPR:$rs1_up),
+ (ins GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
+ opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
bits<5> simm5;
bits<2> uimm2;
- let imm12{11-7} = funct5;
- let imm12{6-5} = uimm2;
- let imm12{4-0} = simm5;
+ let Inst{31-27} = funct5;
+ let Inst{26-25} = uimm2;
+ let Inst{24-20} = simm5;
let Constraints = "$rs1_up = $rs1";
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
index 843a4617f4e1bb..9e98434756b207 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
@@ -70,12 +70,12 @@ class RVKByteSelect<bits<5> funct5, string opcodestr>
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVKUnary_rnum<bits<7> funct7, bits<3> funct3, string opcodestr>
- : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, rnum:$rnum),
- opcodestr, "$rd, $rs1, $rnum">{
+ : RVInstIBase<funct3, OPC_OP_IMM, (outs GPR:$rd),
+ (ins GPR:$rs1, rnum:$rnum), opcodestr, "$rd, $rs1, $rnum"> {
bits<4> rnum;
- let imm12{11-5} = funct7;
- let imm12{4} = 0b1;
- let imm12{3-0} = rnum;
+ let Inst{31-25} = funct7;
+ let Inst{24} = 0b1;
+ let Inst{23-20} = rnum;
}
//===----------------------------------------------------------------------===//
More information about the llvm-commits
mailing list