[PATCH] D156709: [RISCVRVVInitUndef] Ignore tied use for partial undef register

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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The purpose of this code is to restrict overlap between source and destination registers.  The tied input register is conceptually part of the destination.  I can't see any reason why we need to prevent a partial undef tied source here, and skipping it reduces register pressure slightly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156709

Files:
  llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
  llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

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