[PATCH] D156689: [mlir][ArmSME] Use memref indices for load and store

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes created this revision.
c-rhodes added reviewers: awarzynski, benmxwl-arm, dcaballe.
c-rhodes added a project: MLIR.
Herald added subscribers: gysit, Dinistro, bviyer, Moerafaat, zero9178, bzcheeseman, ThomasRaoux, sdasgup3, wenzhicui, wrengr, jsetoain, cota, teijeong, rdzhabarov, tatianashp, msifontes, jurahul, Kayjukh, grosul1, Joonsoo, liufengdb, aartbik, mgester, arpith-jacob, antiagainst, shauheen, rriddle, mehdi_amini, kristof.beyls.
Herald added a reviewer: aartbik.
Herald added a reviewer: ftynse.
Herald added a project: All.
c-rhodes requested review of this revision.
Herald added a reviewer: nicolasvasilache.
Herald added subscribers: stephenneuendorffer, nicolasvasilache.

This patch extends the ArmSME load and store op lowering to use the
memref indices. An integration test that loads two 32-bit element ZA
tiles from memory and stores them back to memory in reverse order to
verify this is added.

Depends on D156467 <https://reviews.llvm.org/D156467>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156689

Files:
  mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
  mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp
  mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir
  mlir/test/Dialect/ArmSME/vector-ops-to-llvm.mlir
  mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir

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