[PATCH] D156685: [RISCV] Match ext_vl + ext_vl + srem + trunc_vl to vrem.vv

[Vettel via Phabricator via llvm-commits]

LWenH created this revision.
LWenH added reviewers: craig.topper, luke, eopXD, frasercrmck.
LWenH added a project: LLVM.
Herald added subscribers: jobnoorman, sameer.abuasal, s.egerton, benna, psnobl, jocewei, the_o, brucehoult, MartinMosbeck, niosHD, sabuasal, johnrusso, hiraditya.
Herald added a project: All.
LWenH requested review of this revision.

This patch match the SDNode Pattern trunc_vl + srem + ext_vl + ext_vl to vrem.vv. This could remove the extra "vsext" and "vnsrl" instructions 
in the case like "c[i] = a[i] % b[i]", where the element type in the array is int8_t and int16_t.

For more test case information, please see :   https://gcc.godbolt.org/z/d6Weo1odf


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156685

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D156685.545603.patch
Type: text/x-patch
Size: 12293 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230731/d4859256/attachment.bin>