[llvm] c4b21d5 - [llc] Add the command line option `-sched-model-force-enable-intervals`.

[Francesco Petrogalli via llvm-commits]

Author: Francesco Petrogalli
Date: 2023-07-31T10:10:18+02:00
New Revision: c4b21d57bc4405e3053223d770a7277c2a358749

URL: https://github.com/llvm/llvm-project/commit/c4b21d57bc4405e3053223d770a7277c2a358749
DIFF: https://github.com/llvm/llvm-project/commit/c4b21d57bc4405e3053223d770a7277c2a358749.diff

LOG: [llc] Add the command line option `-sched-model-force-enable-intervals`.

The option is used to force the use of resource intervals
in the machine scheduler, effectively ignoring the value of
`EnableIntervals` in the instance of the `SchedMachineModel`.

Reviewed By: anemet

Differential Revision: https://reviews.llvm.org/D156540

Added: 
    llvm/test/CodeGen/AArch64/force-enable-intervals.mir

Modified: 
    llvm/include/llvm/CodeGen/TargetSchedule.h
    llvm/lib/CodeGen/TargetSchedule.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/TargetSchedule.h b/llvm/include/llvm/CodeGen/TargetSchedule.h
index bfab9cb92a3850..3d39798790cdce 100644
--- a/llvm/include/llvm/CodeGen/TargetSchedule.h
+++ b/llvm/include/llvm/CodeGen/TargetSchedule.h
@@ -90,7 +90,7 @@ class TargetSchedModel {
   bool hasInstrSchedModelOrItineraries() const {
     return hasInstrSchedModel() || hasInstrItineraries();
   }
-  bool enableIntervals() const { return SchedModel.EnableIntervals; }
+  bool enableIntervals() const;
   /// Identify the processor corresponding to the current subtarget.
   unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
 

diff  --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp
index dba84950f49d45..3cedb38de2ad8d 100644
--- a/llvm/lib/CodeGen/TargetSchedule.cpp
+++ b/llvm/lib/CodeGen/TargetSchedule.cpp
@@ -36,6 +36,10 @@ static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
   cl::desc("Use InstrItineraryData for latency lookup"));
 
+static cl::opt<bool> ForceEnableIntervals(
+    "sched-model-force-enable-intervals", cl::Hidden, cl::init(false),
+    cl::desc("Force the use of resource intervals in the schedule model"));
+
 bool TargetSchedModel::hasInstrSchedModel() const {
   return EnableSchedModel && SchedModel.hasInstrSchedModel();
 }
@@ -341,3 +345,9 @@ TargetSchedModel::computeReciprocalThroughput(const MCInst &MI) const {
   return computeReciprocalThroughput(MI.getOpcode());
 }
 
+bool TargetSchedModel::enableIntervals() const {
+  if (ForceEnableIntervals)
+    return true;
+
+  return SchedModel.EnableIntervals;
+}

diff  --git a/llvm/test/CodeGen/AArch64/force-enable-intervals.mir b/llvm/test/CodeGen/AArch64/force-enable-intervals.mir
new file mode 100644
index 00000000000000..98bee7a579c05a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/force-enable-intervals.mir
@@ -0,0 +1,69 @@
+# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
+# RUN:  -misched-dump-reserved-cycles=true \
+# RUN:  -run-pass=machine-scheduler -debug-only=machine-scheduler \
+# RUN:  -o - %s 2>&1 -misched-topdown| FileCheck %s 
+
+# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
+# RUN:  -misched-dump-reserved-cycles=true -sched-model-force-enable-intervals=true \
+# RUN:  -run-pass=machine-scheduler -debug-only=machine-scheduler \
+# RUN:  -o - %s 2>&1 -misched-topdown| FileCheck %s  --check-prefix=FORCE
+
+# REQUIRES: asserts, aarch64-registered-target
+---
+name: f
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0, $x10
+    $x1 = ADDXrr $x0, $x0
+    $x2 = ADDXrr $x1, $x1
+    $x3 = ADDXrr $x2, $x2
+    STRXui $x3, $x10, 1 :: (store (s64))
+
+
+# CHECK-LABEL: Scheduling SU(3) STRXui $x3, $x10, 1 :: (store (s64))
+# CHECK-NEXT:   Ready @5c
+# CHECK-NEXT:   CortexA55UnitSt +1x2u
+# CHECK-NEXT:   TopQ.A TopLatency SU(3) 5c
+# CHECK-NEXT: TopQ.A @5c
+# CHECK-NEXT:   Retired: 4
+# CHECK-NEXT:   Executed: 5c
+# CHECK-NEXT:   Critical: 2c, 4 MOps
+# CHECK-NEXT:   ExpectedLatency: 5c
+# CHECK-NEXT:   - Latency limited.
+# CHECK-NEXT: CortexA55UnitALU(0) = 3
+# CHECK-NEXT: CortexA55UnitALU(1) = 4294967295
+# CHECK-NEXT: CortexA55UnitB(0) = 4294967295
+# CHECK-NEXT: CortexA55UnitDiv(0) = 4294967295
+# CHECK-NEXT: CortexA55UnitFPALU(0) = 4294967295
+# CHECK-NEXT: CortexA55UnitFPALU(1) = 4294967295
+# CHECK-NEXT: CortexA55UnitFPDIV(0) = 4294967295
+# CHECK-NEXT: CortexA55UnitFPMAC(0) = 4294967295
+# CHECK-NEXT: CortexA55UnitFPMAC(1) = 4294967295
+# CHECK-NEXT: CortexA55UnitLd(0) = 4294967295
+# CHECK-NEXT: CortexA55UnitMAC(0) = 4294967295
+# CHECK-NEXT: CortexA55UnitSt(0) = 6
+
+
+# FORCE-LABEL: Scheduling SU(3) STRXui $x3, $x10, 1 :: (store (s64))
+# FORCE-NEXT:   Ready @5c
+# FORCE-NEXT:   CortexA55UnitSt +1x2u
+# FORCE-NEXT:   TopQ.A TopLatency SU(3) 5c
+# FORCE-NEXT: TopQ.A @5c
+# FORCE-NEXT:   Retired: 4
+# FORCE-NEXT:   Executed: 5c
+# FORCE-NEXT:   Critical: 2c, 4 MOps
+# FORCE-NEXT:   ExpectedLatency: 5c
+# FORCE-NEXT:   - Latency limited.
+# FORCE-NEXT: CortexA55UnitALU(0) = { [0, 3), }
+# FORCE-NEXT: CortexA55UnitALU(1) = { }
+# FORCE-NEXT: CortexA55UnitB(0) = { }
+# FORCE-NEXT: CortexA55UnitDiv(0) = { }
+# FORCE-NEXT: CortexA55UnitFPALU(0) = { }
+# FORCE-NEXT: CortexA55UnitFPALU(1) = { }
+# FORCE-NEXT: CortexA55UnitFPDIV(0) = { }
+# FORCE-NEXT: CortexA55UnitFPMAC(0) = { }
+# FORCE-NEXT: CortexA55UnitFPMAC(1) = { }
+# FORCE-NEXT: CortexA55UnitLd(0) = { }
+# FORCE-NEXT: CortexA55UnitMAC(0) = { }
+# FORCE-NEXT: CortexA55UnitSt(0) = { [5, 6), }