[PATCH] D156642: libunwind: riscv: disable vector test when __riscv_v not defined

[Sean Cross via Phabricator via llvm-commits]

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The commit ca0b4d58eaad405ea74b4db82ecb14b3cfdeccb7 <https://reviews.llvm.org/rGca0b4d58eaad405ea74b4db82ecb14b3cfdeccb7> (https://reviews.llvm.org/D136264) added a code path that uses the `csrr` instruction to read the vector length. This works fine when compiling under risc-v with the -g arch, such as rv32gc or rv64gc. However, depending on the vintage of the compiler, it does not work when compiling with an arch such as riscv32imac.

Older versions of the spec add csr instructions by default, but newer versions of the spec removed those instructions. This means that this file needs to be compiled under `rv32imac` or `rv32imac_zicsr` depending on the compiler version.

This patch adds a check for `__riscv_v` as a compiler define. Because the -V extension came out after the architecture rename to _zicsr, this patch will continue to work on newer compilers.

https://reviews.llvm.org/D136264#4545515


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156642

Files:
  libunwind/src/Registers.hpp


Index: libunwind/src/Registers.hpp
===================================================================
--- libunwind/src/Registers.hpp
+++ libunwind/src/Registers.hpp
@@ -4101,11 +4101,13 @@
     return 0;
   if ((regNum > 0) && (regNum < 32))
     return _registers[regNum];
+#if defined(__riscv_v)
   if (regNum == UNW_RISCV_VLENB) {
     reg_t vlenb;
     __asm__("csrr %0, 0xC22" : "=r"(vlenb));
     return vlenb;
   }
+#endif
   _LIBUNWIND_ABORT("unsupported riscv register");
 }
 


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