[llvm] 14e0a67 - [CSKY] Add more IR patterns to select FNMUL
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 30 21:13:23 PDT 2023
Author: Ben Shi
Date: 2023-07-31T12:12:56+08:00
New Revision: 14e0a67a2d43b6e44032e8df788f43822da6fd71
URL: https://github.com/llvm/llvm-project/commit/14e0a67a2d43b6e44032e8df788f43822da6fd71
DIFF: https://github.com/llvm/llvm-project/commit/14e0a67a2d43b6e44032e8df788f43822da6fd71.diff
LOG: [CSKY] Add more IR patterns to select FNMUL
Reviewed By: zixuan-wu
Differential Revision: https://reviews.llvm.org/D155169
Added:
Modified:
llvm/lib/Target/CSKY/CSKYInstrInfoF1.td
llvm/lib/Target/CSKY/CSKYInstrInfoF2.td
llvm/test/CodeGen/CSKY/fpu/base-d.ll
llvm/test/CodeGen/CSKY/fpu/base-f.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfoF1.td b/llvm/lib/Target/CSKY/CSKYInstrInfoF1.td
index 819e4f039fdd9a..2b6ad9f170b092 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfoF1.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfoF1.td
@@ -141,6 +141,16 @@ defm FCMPZUO : FT_CMPZX<0b001011, "fcmpzuo">;
defm FRECIP : FT_MOV<0b011001, "frecip">;
+// multiplication
+let Predicates = [HasFPUv2_SF] in {
+ def : Pat<(f32 (fmul (fneg sFPR32Op:$vrx), sFPR32Op:$vry)),
+ (FNMUL_S sFPR32Op:$vrx, sFPR32Op:$vry)>;
+}
+let Predicates = [HasFPUv2_DF] in {
+ def : Pat<(f64 (fmul (fneg sFPR64Op:$vrx), sFPR64Op:$vry)),
+ (FNMUL_D sFPR64Op:$vrx, sFPR64Op:$vry)>;
+}
+
//fmov, fmtvr, fmfvr
defm FMOV : FT_MOV<0b000100, "fmov">;
def FMFVRL : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR32Op:$vrx),
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfoF2.td b/llvm/lib/Target/CSKY/CSKYInstrInfoF2.td
index 23c5593181e286..a9f8d5479bd2fd 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfoF2.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfoF2.td
@@ -208,6 +208,16 @@ defm f2FNMULS : F2_XYZZ_T<0b010101, "fnmuls",
defm f2FNMUL : F2_XYZ_T<0b010001, "fnmul",
BinOpFrag<(fneg (fmul node:$LHS, node:$RHS))>>;
+// multiplication
+let Predicates = [HasFPUv3_SF] in {
+ def : Pat<(f32 (fmul (fneg FPR32Op:$vrx), FPR32Op:$vry)),
+ (f2FNMUL_S FPR32Op:$vrx, FPR32Op:$vry)>;
+}
+let Predicates = [HasFPUv3_DF] in {
+ def : Pat<(f64 (fmul (fneg FPR64Op:$vrx), FPR64Op:$vry)),
+ (f2FNMUL_D FPR64Op:$vrx, FPR64Op:$vry)>;
+}
+
// fcvt
def f2FFTOS32_S : F2_XZ_P<0b01000, 0b011011, "fftoi.f32.s32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
def f2FFTOU32_S : F2_XZ_P<0b01000, 0b011010, "fftoi.f32.u32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
diff --git a/llvm/test/CodeGen/CSKY/fpu/base-d.ll b/llvm/test/CodeGen/CSKY/fpu/base-d.ll
index d2d434631f62c2..9b25680a03a474 100644
--- a/llvm/test/CodeGen/CSKY/fpu/base-d.ll
+++ b/llvm/test/CodeGen/CSKY/fpu/base-d.ll
@@ -27,7 +27,7 @@ define double @FADD_DOUBLE_I(double %x) {
; CHECK-DF-NEXT: rts16
; CHECK-DF-NEXT: .p2align 1
; CHECK-DF-NEXT: # %bb.1:
-; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .p2align 2, 0x0
; CHECK-DF-NEXT: .LCPI1_0:
; CHECK-DF-NEXT: .quad 0xbff0000000000000 # double -1
;
@@ -38,7 +38,7 @@ define double @FADD_DOUBLE_I(double %x) {
; CHECK-DF2-NEXT: rts16
; CHECK-DF2-NEXT: .p2align 1
; CHECK-DF2-NEXT: # %bb.1:
-; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .p2align 2, 0x0
; CHECK-DF2-NEXT: .LCPI1_0:
; CHECK-DF2-NEXT: .quad 0xbff0000000000000 # double -1
entry:
@@ -72,7 +72,7 @@ define double @FSUB_DOUBLE_I(double %x) {
; CHECK-DF-NEXT: rts16
; CHECK-DF-NEXT: .p2align 1
; CHECK-DF-NEXT: # %bb.1:
-; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .p2align 2, 0x0
; CHECK-DF-NEXT: .LCPI3_0:
; CHECK-DF-NEXT: .quad 0x3ff0000000000000 # double 1
;
@@ -83,7 +83,7 @@ define double @FSUB_DOUBLE_I(double %x) {
; CHECK-DF2-NEXT: rts16
; CHECK-DF2-NEXT: .p2align 1
; CHECK-DF2-NEXT: # %bb.1:
-; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .p2align 2, 0x0
; CHECK-DF2-NEXT: .LCPI3_0:
; CHECK-DF2-NEXT: .quad 0x3ff0000000000000 # double 1
@@ -108,29 +108,62 @@ entry:
ret double %fmul
}
+define double @FNMUL_DOUBLE_a(double %x, double %y) {
+;
+; CHECK-DF-LABEL: FNMUL_DOUBLE_a:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fnmuld vr0, vr1, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FNMUL_DOUBLE_a:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fnmul.64 vr0, vr1, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %z = fneg double %y
+ %fnmul = fmul double %z, %x
+ ret double %fnmul
+}
+
+define double @FNMUL_DOUBLE_b(double %x, double %y) {
+; CHECK-DF-LABEL: FNMUL_DOUBLE_b:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fnmuld vr0, vr0, vr1
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FNMUL_DOUBLE_b:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fnmul.64 vr0, vr0, vr1
+; CHECK-DF2-NEXT: rts16
+entry:
+ %z = fneg double %x
+ %fnmul = fmul double %y, %z
+ ret double %fnmul
+}
+
define double @FMUL_DOUBLE_I(double %x) {
;
; CHECK-DF-LABEL: FMUL_DOUBLE_I:
; CHECK-DF: # %bb.0: # %entry
-; CHECK-DF-NEXT: grs32 a0, .LCPI5_0
+; CHECK-DF-NEXT: grs32 a0, .LCPI7_0
; CHECK-DF-NEXT: fldd vr1, (a0, 0)
; CHECK-DF-NEXT: fmuld vr0, vr0, vr1
; CHECK-DF-NEXT: rts16
; CHECK-DF-NEXT: .p2align 1
; CHECK-DF-NEXT: # %bb.1:
-; CHECK-DF-NEXT: .p2align 2
-; CHECK-DF-NEXT: .LCPI5_0:
+; CHECK-DF-NEXT: .p2align 2, 0x0
+; CHECK-DF-NEXT: .LCPI7_0:
; CHECK-DF-NEXT: .quad 0xc01c000000000000 # double -7
;
; CHECK-DF2-LABEL: FMUL_DOUBLE_I:
; CHECK-DF2: # %bb.0: # %entry
-; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI5_0]
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI7_0]
; CHECK-DF2-NEXT: fmul.64 vr0, vr0, vr1
; CHECK-DF2-NEXT: rts16
; CHECK-DF2-NEXT: .p2align 1
; CHECK-DF2-NEXT: # %bb.1:
-; CHECK-DF2-NEXT: .p2align 2
-; CHECK-DF2-NEXT: .LCPI5_0:
+; CHECK-DF2-NEXT: .p2align 2, 0x0
+; CHECK-DF2-NEXT: .LCPI7_0:
; CHECK-DF2-NEXT: .quad 0xc01c000000000000 # double -7
entry:
%fmul = fmul double %x, -7.0
@@ -159,25 +192,25 @@ define double @FDIV_DOUBLE_I(double %x) {
;
; CHECK-DF-LABEL: FDIV_DOUBLE_I:
; CHECK-DF: # %bb.0: # %entry
-; CHECK-DF-NEXT: grs32 a0, .LCPI7_0
+; CHECK-DF-NEXT: grs32 a0, .LCPI9_0
; CHECK-DF-NEXT: fldd vr1, (a0, 0)
; CHECK-DF-NEXT: fdivd vr0, vr0, vr1
; CHECK-DF-NEXT: rts16
; CHECK-DF-NEXT: .p2align 1
; CHECK-DF-NEXT: # %bb.1:
-; CHECK-DF-NEXT: .p2align 2
-; CHECK-DF-NEXT: .LCPI7_0:
+; CHECK-DF-NEXT: .p2align 2, 0x0
+; CHECK-DF-NEXT: .LCPI9_0:
; CHECK-DF-NEXT: .quad 0xc01c000000000000 # double -7
;
; CHECK-DF2-LABEL: FDIV_DOUBLE_I:
; CHECK-DF2: # %bb.0: # %entry
-; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI7_0]
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI9_0]
; CHECK-DF2-NEXT: fdiv.64 vr0, vr0, vr1
; CHECK-DF2-NEXT: rts16
; CHECK-DF2-NEXT: .p2align 1
; CHECK-DF2-NEXT: # %bb.1:
-; CHECK-DF2-NEXT: .p2align 2
-; CHECK-DF2-NEXT: .LCPI7_0:
+; CHECK-DF2-NEXT: .p2align 2, 0x0
+; CHECK-DF2-NEXT: .LCPI9_0:
; CHECK-DF2-NEXT: .quad 0xc01c000000000000 # double -7
entry:
%fdiv = fdiv double %x, -7.0
diff --git a/llvm/test/CodeGen/CSKY/fpu/base-f.ll b/llvm/test/CodeGen/CSKY/fpu/base-f.ll
index cd43cc451716ab..041dbd3dc51d27 100644
--- a/llvm/test/CodeGen/CSKY/fpu/base-f.ll
+++ b/llvm/test/CodeGen/CSKY/fpu/base-f.ll
@@ -144,6 +144,40 @@ entry:
ret float %fmul
}
+define float @fnmulRR_a(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fnmulRR_a:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fnmuls vr0, vr1, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fnmulRR_a:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fnmul.32 vr0, vr1, vr0
+; CHECK-SF2-NEXT: rts16
+
+entry:
+ %z = fneg float %y
+ %fnmul = fmul float %z, %x
+ ret float %fnmul
+}
+
+define float @fnmulRR_b(float %x, float %y) {
+; CHECK-SF-LABEL: fnmulRR_b:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fnmuls vr0, vr0, vr1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fnmulRR_b:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fnmul.32 vr0, vr0, vr1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %z = fneg float %x
+ %fnmul = fmul float %y, %z
+ ret float %fnmul
+}
+
define float @fmulRI(float %x) {
;
; CHECK-SF-LABEL: fmulRI:
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