[PATCH] D156614: [AArch64][GISel] Handling for G_VECREDUCE_FMIN and G_VECREDUCE_FMAX

[Thorsten via Phabricator via llvm-commits]

tschuett added a comment.

You could argue that the assembler show that importing works as expected and you find `fmaxnmv` now. But they are also end-to-end tests. They go from LLVM IR to assembler while visiting the IR translator, the legalizer, regbandk select, and maybe instruction selection. A legalize-vecreduce.mir with MIR tests might help you to prove that your legalization strategy works in isolation. IDK how far you can go with a select-vecreduce.mir to test the selection in isolation.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156614/new/

https://reviews.llvm.org/D156614