[PATCH] D156614: [AArch64][GISel] Handling for G_VECREDUCE_FMIN and G_VECREDUCE_FMAX
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 30 06:53:13 PDT 2023
dmgreen created this revision.
dmgreen added reviewers: aemerson, stuij, samtebbs, arsenm, tschuett, chuongg3.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
dmgreen requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.
This adds legalization for G_VECREDUCE_FMIN and G_VECREDUCE_FMAX, where the selection can go via tablegen patterns. I haven't tried to get non-power2 types working yet, just the more legal types.
https://reviews.llvm.org/D156614
Files:
llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
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