[PATCH] D138809: [RISCV] Support vector crypto extension LLVM IR

[Brandon Wu via Phabricator via llvm-commits]

4vtomat added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1551
       return selectVSETVLI(Node);
+    case Intrinsic::riscv_vrol: {
+      SDValue Merge = Node->getOperand(1);
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craig.topper wrote:
> This seems unnecessarily complex. https://reviews.llvm.org/D155439 already did this for non-intrinsics using an SDNodeXForm in tablegen
Oh, that's much better, thanks!


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7261
+  case Intrinsic::riscv_vsm4r_vs: {
+    assert(isValidEGW(4, Op.getSimpleValueType()) &&
+           isValidEGW(4, Op->getOperand(1).getSimpleValueType()) &&
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craig.topper wrote:
> This assert isn't helpful to compiler users. It's not part of release builds.
Oh, ok. I just changed it to report_fatal_error~


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:7340
+  defm : VPatBinaryV_VV_VX<"int_riscv_vrol", "PseudoVROL", AllIntegerVectors>;
+  defm : VPatBinaryV_VV_VX_VI<"int_riscv_vror", "PseudoVROR", AllIntegerVectors>;
+  defm : VPatBinaryW_VV_VX_VI<"int_riscv_vwsll", "PseudoVWSLL", AllWidenableIntVectors>;
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craig.topper wrote:
> VPatBinaryV_VV_VX_VI defaults simm5, but vror.vi uses uimm6.
Oh, I forgot this instruction has different encoding of immediate, thanks!


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td:678
+multiclass VPatBinaryV_VI_NoMask<string intrinsic, string instruction,
+                          list<VTypeInfo> vtilist, Operand imm_type = timm5> {
+  foreach vti = vtilist in
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craig.topper wrote:
> timm5 uses isInt<5>, but I think you want isUInt<5>?
Oh, correct, thanks!


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138809/new/

https://reviews.llvm.org/D138809