[PATCH] D156311: [AArch64][SME2][SVE2p1] Choose strided or contiguous loads

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau created this revision.
MattDevereau added reviewers: sdesmalen, david-arm, dtemirbulatov.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
MattDevereau requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Lower to the strided/contiguous addressing mode of
ld1/ldnt1 instructions depending on register allocation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156311

Files:
  llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sme2-intrinsics-ld1.ll
  llvm/test/CodeGen/AArch64/sme2-intrinsics-ldnt1.ll

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