[PATCH] D156099: [AMDGPU] Add True16 register classes.

[Joe Nash via Phabricator via llvm-commits]

Joe_Nash added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:602
+}
+
+def VGPR_16 : SIRegisterClass<"AMDGPU",  Reg16Types.types, 16,
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I think the comment downstream about which instruction types use which types of Registers is helpful.


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Comment at: llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir:31
   ; CHECK-NEXT:   [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load (s32), addrspace 3)
-  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_HI16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
-  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VGPR_HI16 */, [[DS_READ_B32_gfx9_]]
-  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_HI16 */, def undef %0.sub0, 851978 /* regdef:VGPR_HI16 */, def undef %0.sub1
+  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
+  ; CHECK-NEXT:   INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_]]
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Unrelated to this patch, but I don't understand the purpose of these tests. It looks like we are referencing register classes by number in the test input. Therefore any time we modify the number of register classes the tests changes their meaning.


Repository:
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  https://reviews.llvm.org/D156099/new/

https://reviews.llvm.org/D156099