[PATCH] D155772: [RISCV][GlobalISel] Legalize bitshift instructions for narrow types that are a power of 2

[Nitin John Raj via Phabricator via llvm-commits]

nitinjohnraj marked an inline comment as not done.
nitinjohnraj added inline comments.


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:59
+      .legalIf(ExtLegalFunc)
+      .clampScalar(0, XLenLLT, XLenLLT); // Just for XLen, others are handled.
+
----------------
tschuett wrote:
> craig.topper wrote:
> > This should be 2*XLen. The AArch64 code says 128 here.
> X86 did it differently, but it does not support vectors:
> https://github.com/llvm/llvm-project/blob/c3648f37d0ed24e5a783d4ead4c34c9f4796b3e3/llvm/lib/Target/X86/X86LegalizerInfo.cpp#L398
This needs to be handled in parent revision.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155772/new/

https://reviews.llvm.org/D155772