[PATCH] D155772: [RISCV][GlobalISel] Legalize bitshift instructions for narrow types that are a power of 2

[Nitin John Raj via Phabricator via llvm-commits]

nitinjohnraj marked an inline comment as done.
nitinjohnraj added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir:3
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
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nitinjohnraj wrote:
> arsenm wrote:
> > Need some < 8 bit and odd intermediate sizes too
> This doesn't work with odd-sized types right now, I'll update the description and fix that in a future patch. 
> 
> I added one test for i1; but in order to pass it, I needed to change the legalization logic for G_{ANY/Z/S}EXT. Specifically, I allowed the SrcSize and DstSize to be as small as 1 for legal instructions. But neither X86 nor AArch64 allows this, so I'm not sure we should be allowing this.
To clarify, I meant it didn't work will odd types less than 8. I'll add a test for an odd type.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155772/new/

https://reviews.llvm.org/D155772