[PATCH] D156350: [X86] Allow pre-SSE41 targets to extract multiple v16i8 elements coming from the same DWORD/WORD super-element

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:20575
+    case X86ISD::PEXTRB:
+    case X86ISD::PEXTRW:
+    case ISD::EXTRACT_VECTOR_ELT:
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goldstein.w.n wrote:
> ZEXT_MOVL too no?
we only need to handle extractions from the vector to gpr - ZEXT_MOVL is the other way around.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:20581
+      }
+      DemandedElts.setBit(User->getConstantOperandVal(1));
+      break;
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goldstein.w.n wrote:
> Shouldn't the number of bits set be a function of the extraction width? I.e id expect `pextrw` to set 2x as many bits as `pextrb` or will it never be legal to have `pextr*` that doesn't match ele width?
That should be handled by recursion via the BITCAST case below - PEXTRW / PEXTRB only work with their own v8i16 / v16i8 types (although tbh we never needed seperate node types - creating a single X86ISD::PEXTR nodetype would have been enough),


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  https://reviews.llvm.org/D156350/new/

https://reviews.llvm.org/D156350