[PATCH] D156350: [X86] Allow pre-SSE41 targets to extract multiple v16i8 elements coming from the same DWORD/WORD super-element

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:20575
+    case X86ISD::PEXTRB:
+    case X86ISD::PEXTRW:
+    case ISD::EXTRACT_VECTOR_ELT:
----------------
ZEXT_MOVL too no?


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:20581
+      }
+      DemandedElts.setBit(User->getConstantOperandVal(1));
+      break;
----------------
Shouldn't the number of bits set be a function of the extraction width? I.e id expect `pextrw` to set 2x as many bits as `pextrb` or will it never be legal to have `pextr*` that doesn't match ele width?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156350/new/

https://reviews.llvm.org/D156350