[PATCH] D156250: [RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td:44
+def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
+          (VT_MASKCN GPR:$rs1, GPR:$rc)>;
 } // Predicates = [IsRV64, HasVendorXVentanaCondOps]
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Should be `VT_MASKC`?


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Comment at: llvm/test/CodeGen/RISCV/condops.ll:1090
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a3, a0
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a1
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This change is strange.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156250/new/

https://reviews.llvm.org/D156250