[PATCH] D156250: [RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc accepted this revision.
wangpc added a comment.
This revision is now accepted and ready to land.

LGTM in general.



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td:32
 let Predicates = [IsRV64, HasVendorXVentanaCondOps] in {
 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
           (VT_MASKC GPR:$rs1, GPR:$rc)>;
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These patterns are almost the same as `zicond`'s, is it possible to remove the redundancy?
(Just a weak suggestion, it's OK to ignore it)


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  https://reviews.llvm.org/D156250/new/

https://reviews.llvm.org/D156250