[PATCH] D156319: [RISCV] Relax ta/ma policy into tu/mu in InsertVSETVLI

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
luke added reviewers: reames, craig.topper.
Herald added subscribers: jobnoorman, asb, pmatos, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
luke requested review of this revision.
Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay.
Herald added a project: LLVM.

Currently, we only allow a vsetvli to be merged with another vsetvli if their
tail and mask policies are exactly the same.
However, an agnostic policy can be replaced with an undisturbed policy, since
it satisfies the requirement that the elements are either left unchanged (or
replaced with all ones).
This patch relaxes the requirement in areCompatibleVTYPEs to allow converting
ta -> tu and ma -> mu. This affects both the top-to-bottom and bottom-to-top
passes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156319

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-costrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
  llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
  llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fround-costrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vmacc.ll
  llvm/test/CodeGen/RISCV/rvv/vmadd.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsac.ll
  llvm/test/CodeGen/RISCV/rvv/vnmsub.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
  llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll