[PATCH] D155928: [RISCV] Add patterns for vnsrl.vx where shift amount is truncated

[Luke Lau via Phabricator via llvm-commits]

luke marked an inline comment as done.
luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:3025
+    selectVLOp(N->getOperand(2), VL);
+    return N->getOperand(1).getOpcode() == RISCVISD::VMSET_VL &&
+           isa<ConstantSDNode>(VL) &&
----------------
craig.topper wrote:
> luke wrote:
> > I thought we would need to check the VL of this VMSET_VL here, but the `true_mask` pattern used in other tablegen patterns doesn't seem to:
> > 
> > ```
> > def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>;
> > ```
> > 
> > Any idea as to why that is?
> I don't remember if it was because it was hard to do in tablegen or just that didn't matter because the bits past VL are undefined.
That makes sense, left a comment about the latter


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  https://reviews.llvm.org/D155928/new/

https://reviews.llvm.org/D155928