[PATCH] D155928: [RISCV] Add patterns for vnsrl.vx where shift amount is truncated

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 544093.
luke added a comment.

Add comments explaining vmset_vl
Check truncation doesn't go below 8 bits (Can this happen?)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155928/new/

https://reviews.llvm.org/D155928

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D155928.544093.patch
Type: text/x-patch
Size: 4931 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230725/14aedcfd/attachment.bin>