[llvm] 1f5a1b8 - [DAGCombiner] Minor improvements to foldAndOrOfSETCC. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 25 00:26:28 PDT 2023
Author: Craig Topper
Date: 2023-07-25T00:20:06-07:00
New Revision: 1f5a1b8952921c39ed0f4a50872990533661278b
URL: https://github.com/llvm/llvm-project/commit/1f5a1b8952921c39ed0f4a50872990533661278b
DIFF: https://github.com/llvm/llvm-project/commit/1f5a1b8952921c39ed0f4a50872990533661278b.diff
LOG: [DAGCombiner] Minor improvements to foldAndOrOfSETCC. NFC
Reduce the scope of some variables.
Replace an if with an assertion.
Reviewed By: kmitropoulou
Differential Revision: https://reviews.llvm.org/D156140
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 0cbf7bd9bd4795..de909cc1079565 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6054,10 +6054,6 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
TLI.isOperationLegal(ISD::SMAX, OpVT) &&
TLI.isOperationLegal(ISD::UMIN, OpVT) &&
TLI.isOperationLegal(ISD::SMIN, OpVT)) {
- SDValue CommonValue;
- SDValue Operand1;
- SDValue Operand2;
- ISD::CondCode CC = ISD::SETCC_INVALID;
if (LHS->getOpcode() == ISD::SETCC && RHS->getOpcode() == ISD::SETCC &&
LHS->hasOneUse() && RHS->hasOneUse() &&
// The two comparisons should have either the same predicate or the
@@ -6065,6 +6061,8 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
(CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR)) &&
// The optimization does not work for `==` or `!=` .
!ISD::isIntEqualitySetCC(CCL) && !ISD::isIntEqualitySetCC(CCR)) {
+ SDValue CommonValue, Operand1, Operand2;
+ ISD::CondCode CC = ISD::SETCC_INVALID;
if (CCL == CCR) {
if (LHS0 == RHS0) {
CommonValue = LHS0;
@@ -6077,7 +6075,8 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) {
Operand2 = RHS0;
CC = CCL;
}
- } else if (CCL == ISD::getSetCCSwappedOperands(CCR)) {
+ } else {
+ assert(CCL == ISD::getSetCCSwappedOperands(CCR) && "Unexpected CC");
if (LHS0 == RHS1) {
CommonValue = LHS0;
Operand1 = LHS1;
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