[PATCH] D156105: [AMDGPU][True16] Support generating differently-sized register transfers.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:740-744
+        MCRegister &RegToFix = (Size == 16) ? DestReg : SrcReg;
+        MCRegister Super = RI.get32BitRegister(RegToFix);
+        assert(RI.getSubReg(Super, AMDGPU::lo16) == RegToFix ||
+               RI.getSubReg(Super, AMDGPU::hi16) == RegToFix);
+        RegToFix = Super;
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arsenm wrote:
> Is this actually reachable? I forget how exactly we ended up with this partial 16-bit register thing
I'm going to try to understand more about what's going on here, but maybe @Joe_Nash already knows the answer as he was working on that bit.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:741
+        MCRegister &RegToFix = (Size == 16) ? DestReg : SrcReg;
+        MCRegister Super = RI.get32BitRegister(RegToFix);
+        assert(RI.getSubReg(Super, AMDGPU::lo16) == RegToFix ||
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rampitec wrote:
> Are these tabs?
Nope, just re-indendting with proper spaces.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156105/new/

https://reviews.llvm.org/D156105