[PATCH] D156131: [LV] Generate predicate in a proper VPBasicBlock
Kolya Panchenko via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 24 07:58:19 PDT 2023
nikolaypanchenko added a comment.
The problem was found in our downstream compiler with masked-ordered reduction enabled, where non-flattened invalid VPlan looks like
REDUCE ir<%add.i> = ir<%add.i2426> + reduce.fadd (ir<%conv.i>, vp<%12>)
Successor(s): if.else.i.i.i.i.i15
if.else.i.i.i.i.i15:
EMIT vp<%12> = or vp<%5> ir<%1>
EMIT vp<%13> = not ir<%0>
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D156131/new/
https://reviews.llvm.org/D156131
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