[PATCH] D156131: [LV] Generate predicate in a proper VPBasicBlock

[Kolya Panchenko via Phabricator via llvm-commits]

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Current implementation generates masks on demand by calling to
`createBlockInMask` function. The function is calling VPBuilder which
uses previously set insertion point. As a result, invalid non-flattened
VPlan is constructed as EdgeMask can be built in destination
VPBasicBlock.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156131

Files:
  llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
  llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
  llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
  llvm/test/Transforms/LoopVectorize/AArch64/tail-fold-uniform-memops.ll
  llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
  llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
  llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
  llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
  llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
  llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
  llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
  llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
  llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
  llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll
  llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll
  llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll
  llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
  llvm/test/Transforms/LoopVectorize/if-reduction.ll
  llvm/test/Transforms/LoopVectorize/induction.ll
  llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
  llvm/test/Transforms/LoopVectorize/load-of-struct-deref-pred.ll
  llvm/test/Transforms/LoopVectorize/pr55167-fold-tail-live-out.ll
  llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
  llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
  llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll
  llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
  llvm/test/Transforms/LoopVectorize/uniform-blend.ll
  llvm/test/Transforms/LoopVectorize/vplan-printing.ll
  llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll