[PATCH] D156111: [LV] Ignore the option prefer-predicate-over-epilogue for target unspported mask

[Allen zhong via Phabricator via llvm-commits]

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If don't specified a target default, the option -prefer-predicate-over-epilogue will be ignored.
then, we can add option -enable-masked-interleaved-mem-accesses to get same behavior as before the changes.

      

Fixes https://github.com/llvm/llvm-project/issues/63977.


https://reviews.llvm.org/D156111

Files:
  llvm/lib/Target/ARM/ARMTargetTransformInfo.h
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
  llvm/test/Transforms/LoopVectorize/reduction-predselect.ll


Index: llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
===================================================================
--- llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
+++ llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=loop-vectorize,dce,instcombine -force-vector-width=4 -force-vector-interleave=1 -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -prefer-predicated-reduction-select -S | FileCheck %s
+; RUN: opt < %s -passes=loop-vectorize,dce,instcombine -force-vector-width=4 -force-vector-interleave=1 -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -prefer-predicated-reduction-select -enable-masked-interleaved-mem-accesses -S | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
 
Index: llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
===================================================================
--- llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
+++ llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=loop-vectorize,dce,instcombine -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S | FileCheck %s
+; RUN: opt < %s -passes=loop-vectorize,dce,instcombine -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -enable-masked-interleaved-mem-accesses -S | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 
Index: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
===================================================================
--- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -9821,7 +9821,10 @@
     case PreferPredicateTy::ScalarEpilogue:
       return CM_ScalarEpilogueAllowed;
     case PreferPredicateTy::PredicateElseScalarEpilogue:
-      return CM_ScalarEpilogueNotNeededUsePredicate;
+      if (useMaskedInterleavedAccesses(*TTI))
+        return CM_ScalarEpilogueNotNeededUsePredicate;
+      else
+        return CM_ScalarEpilogueAllowed;
     case PreferPredicateTy::PredicateOrDontVectorize:
       return CM_ScalarEpilogueNotAllowedUsePredicate;
     };
Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -79,6 +79,9 @@
 
   bool shouldExpandReduction(const IntrinsicInst *II) const;
   bool supportsScalableVectors() const { return ST->hasVInstructions(); }
+  bool enableMaskedInterleavedAccessVectorization() const {
+    return ST->hasVInstructions();
+  }
   bool enableOrderedReductions() const { return true; }
   bool enableScalableVectorization() const { return ST->hasVInstructions(); }
   TailFoldingStyle
Index: llvm/lib/Target/ARM/ARMTargetTransformInfo.h
===================================================================
--- llvm/lib/Target/ARM/ARMTargetTransformInfo.h
+++ llvm/lib/Target/ARM/ARMTargetTransformInfo.h
@@ -308,6 +308,9 @@
                                 TargetLibraryInfo *LibInfo,
                                 HardwareLoopInfo &HWLoopInfo);
   bool preferPredicateOverEpilogue(TailFoldingInfo *TFI);
+  bool enableMaskedInterleavedAccessVectorization() const {
+    return ST->hasMVEIntegerOps();
+  }
   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                                TTI::UnrollingPreferences &UP,
                                OptimizationRemarkEmitter *ORE);


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